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參數(shù)資料
| 型號： | AD9846AJSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC 10BIT 48LQFP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
REV. 0
AD9846A
–14–
SDATA
SCK
SL
RNW
TEST BIT
0
A2
0
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
tDS
tDH
tLS
tLH
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
Figure 21. Serial Write Operation
SDATA
SCK
SL
RNW
TEST BIT
10
0
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
tDS
tDH
tLS
tLH
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE FIFTH SCK FALLING EDGE, AND IS UPDATED ON
SCK FALLING EDGES.
tDV
Figure 22. Serial Readback Operation
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Table I. Internal Register Map
Register
Address
Data Bits
Name
A0 A1 A2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
Operation
0
Channel Select Power-Down
Software
OB Clamp
0
*
1
**
0
*
0
*
0
*
CCD/AUX1/2 Modes
Reset
On/Off
VGA Gain
1
0
LSB
MSB
X
Clamp Level
0
1
0
LSB
MSB
X
Control
1
0
Color Steering Mode
PxGA
Clock Polarity Select for
0
*
0
*
Three-
X
Selection
On/Off
SHP/SHD/CLP/DATA
State
PxGA Gain0
0
1
LSB
MSB
X
PxGA Gain1
1
0
1
LSB
MSB
X
PxGA Gain2
0
1
LSB
MSB
X
PxGA Gain3
1
LSB
MSB
X
*Internal use only. Must be set to zero.
**Must be set to one.
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