PIXEL GAIN AMPLIFIER (PxGA) TIMING FRAME n VD HD LINE 0 LINE 1 LINE 2 LINE m 0101... 2323... 0101... LINE m–1 LINE 0 LINE 1" />
參數(shù)資料
型號(hào)： AD9846AJSTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/24頁(yè)
文件大小： 0K
描述： IC CCD SIGNAL PROC 10BIT 48LQFP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 2,000
類(lèi)型： CCD 信號(hào)處理器，10 位
輸入類(lèi)型： 邏輯
輸出類(lèi)型： 邏輯
接口： 3 線串口
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
REV. 0
AD9846A
–10–
PIXEL GAIN AMPLIFIER (PxGA) TIMING
FRAME n
VD
HD
LINE 0
LINE 1
LINE 2
LINE m
0101...
2323...
0101...
LINE m–1
LINE 0
LINE 1
LINE 2
LINE m
0101...
2323...
0101...
LINE m–1
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
FRAME n+1
Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence
SHP
HD
3ns MIN
PxGA GAIN
GAIN0
GAIN1
GAIN0
GAIN3
GAIN2
GAINX
VD
NOTES:
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
5 PIXEL MIN
Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing
0101...
2323...
0101...
2323...
0101...
HD
LINE 0
LINE 1
LINE 2
LINE m
LINE m–1
LINE 0
LINE 1
LINE 2
LINE m
LINE m–1
EVEN FIELD
ODD FIELD
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
VD
Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
SHP
HD
PxGA GAIN
3ns MIN
5 PIXEL MIN
VD
GAIN0
GAIN1
GAIN0
GAIN3
GAIN2
GAINX
Figure 11. PxGA Mode 2 (Interlace) Detailed Timing
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