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| 型號(hào)： | AD9772AAST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 14-BIT DAC, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁(yè)數(shù)： | 22/32頁(yè) |
| 文件大?。?/td> | 596K |
| 代理商： | AD9772AAST |
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REV. A
AD9772A
–22–
APPLICATIONS
MULTICARRIER
The AD9772A
’
s wide dynamic range performance makes it well
suited for next generation base station applications in which it
reconstructs multiple modulated carriers over a designated
frequency band. Cellular multicarrier and multimode radios are
often referred to as software radios since the carrier tuning and
modulation scheme is software programmable and performed
digitally. The AD9772A is the recommended TxDAC in
Analog Device
’
s SoftCell chipset which comprises the AD6622,
Quadrature Digital Upconverter IC, along with its compan-
ion Rx Digital Downconverter IC, the AD6624, and 14-bit,
65 MSPS ADC, the AD6644. Figure 30 shows a generic soft-
ware radio Tx signal chain based on the AD9772A/AD6622.
Figure 31 shows a spectral plot of the AD9772A operating at
64.54 MSPS reconstructing eight IS-136 modulated carriers
spread over a 25 MHz band. For this particular test scenario,
the AD9772A exhibited 74 dBc SFDR performance along with
a carrier-to-noise ratio (CNR) of 73 dB. Figure 32 shows a spectral
plot of the AD9772A operating at 52 MSPS reconstructing four
equal GSM carriers spread over a 15 MHz band. The SFDR
and CNR (in 100 kHz BW) measured to be 76 dBc and 83.4 dB
respectively along with a channel power of
–
13.5 dBFS. Note,
the test vectors were generated using Rohde & Schwarz
’
s
WinIQSIM software.
JTAG
OTHER AD6622s FOR
INCREASED CHANNEL
CAPACITY
AD9772A
PLLLOCK
CLK
SUMMATION
SPORT
RCF
CIC
FILTER
NCO
QAM
SPORT
RCF
CIC
FILTER
NCO
QAM
SPORT
RCF
CIC
FILTER
NCO
QAM
SPORT
RCF
CIC
FILTER
NCO
QAM
CLK
PORT
AD6622
Figure 30. Generic Multicarrier Signal Chain Using the
AD6622 and AD9772A
FREQUENCY
–
MHz
–
40
–
50
–
100
0
A
–
–
60
–
70
–
80
–
90
5
10
15
20
30
25
–
30
–
20
Figure 31. Spectral Plot of AD9772A Reconstructing
Eight IS-136 Modulated Carriers @ f
DATA
= 64.54 MSPS,
PLLVDD = 0
FREQUENCY
–
MHz
–
10
–
110
0
A
–
–
30
–
50
–
70
–
90
5
10
15
20
25
–
100
–
80
–
60
–
40
–
20
Figure 32. Spectral Plot of AD9772A Reconstructing
Four GSM Modulated Carriers @ f
DATA
= 52 MSPS,
PLLVDD = 0
Although the above IS-136 and GSM spectral plots are repre-
sentative of the AD9772A
’
s performance for a particular set of
test conditions, the following recommendations are offered to
maximize the performance and system integration of the AD9772A
into multicarrier applications:
1. To achieve the highest possible CNR, the PLL Clock Multi-
plier should be disabled (i.e., PLLVDD to PLLCOM) and
the AD9772A
’
s clock input driven with a low jitter/phase
noise clock source at twice the input data rate. In this case,
the divide-by-two clock appearing at PLLLOCK should
serve as the master clock for the digital upconverter IC(s)
such as the AD6622. PLLLOCK should be limited to a
fanout of one.
2. The AD9772A achieves its optimum noise and distortion
performance when configured for baseband operation along
with a differential output and a full-scale current, I
OUTFS
,
set to approximately 20 mA.
3. Although the 2 interpolation filters frequency roll-off pro-
vides a maximum reconstruction bandwidth of 0.422
the optimum adjacent image rejection (due to the interpola-
tion process) is achieved (i.e., > 73 dBc) if the maximum
channel assignment is kept below 0.400
4. To simplify the subsequent IF stages filter requirements (i.e.,
mixer image and LO rejection), it is often advantageous to
offset the frequency band from dc to relax the transition band
requirements of the IF filter.
5. Oversampling the frequency band often results in improved
SFDR and CNR performance. This implies that the data
input rate to the AD9772A is greater than f
PASSBAND
/0.4
where f
PASSBAND
is the maximum bandwidth in which the
AD9772A will be required to reconstruct and place carriers.
The improved noise performance results in a reduction in
the TxDAC
’
s noise spectral density due to the added process
gain realized with oversampling. Also, higher oversampling
ratios provide greater flexibility in the frequency planning.
f
DATA,
f
DATA.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9772AASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP T/R |
| AD9772AASTZ | 功能描述:IC DAC 14BIT 160MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AD9772AASTZRL | 功能描述:IC DAC 14BIT 160MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9772A-EB | 制造商:Analog Devices 功能描述:14 BIT DAC W/2X INTERPOLATION 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9772A - Bulk |
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