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參數(shù)資料
| 型號： | AD9772AAST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 14-BIT DAC, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 596K |
| 代理商： | AD9772AAST |
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REV. A
AD9772A
–15–
latched into the AD9772 on every other rising edge of the differ-
ential clock input. The rising edge that corresponds to the input
latch immediately precedes the rising edge of the 1 clock at
PLLLOCK. Adequate setup and hold time for the input data as
shown in Figure 1b should be allowed. Note that enough delay
is present between CLK+/CLK
–
and the data input latch to
cause the minimum setup time for input data to be negative.
This is noted in the Digital Specifications section. PLLLOCK
contains a relatively weak driver output, with its output delay
(t
OD
) sensitive to output capacitance loading. Thus PLLLOCK
should be buffered for fanouts greater than one, and/or load
capacitance greater than 10 pF. If a data timing issue exists
between the AD9772A and its external driver device, the 1
clock appearing at PLLLOCK can be inverted via an external
gate to ensure proper setup and hold time.
CHARGE
PUMP
PHASE
DETECTOR
EXT/INT
CLOCK CONTROL
PRESCALER
CLKVDD
OUT1
CLKCOM
MOD1 MOD0 RESET
CLK+
LPF
PLL
VDD
PLL
COM
DIV1
DIV0
CLOCK
DISTRIBUTION
–
+
PLLLOCK
CLK
–
VCO
AD9772A
Figure 11. Clock Multiplier with PLL Clock Multiplier
Disabled
SYNCHRONIZATION OF CLK/DATA USING RESET WITH
PLL DISABLED
The relationship between the internal and external clocks in this
mode is shown in Figure 12. A clock at the output update data
rate (2 the input data rate) must be applied to the CLK in-
puts. Internal dividers create the internal 1 clock necessary for
the input latches. With the PLL disabled, a delayed version of the
1 clock is present at the PLLLOCK pin. The DAC latch is
updated on the particular rising edge of the external 2 clock
which corresponds to the rising edge of the 1 clock. Updates
to the input data should be synchronized to this specific rising
edge as shown in Figure 12. To ensure this synchronization, a
Logic 1 should be momentarily applied to the RESET pin on
power up, before CLK is applied. Applying a momentary Logic 1
to RESET brings the 1 clock at PLLLOCK to a Logic 1. On
the next rising edge of the 2 clock, the 1 clock will go to
Logic 0. The following rising edge of the 2 clock will cause
the 1 clock to Logic 1 again, as well as update the data in
both of the input latches.
DIGITAL DATA IN
EXTERNAL
2
CLK
DELAYED INTERNAL
1 CLK
LOAD DEPENDENT
DELAYED 1 CLK
AT PLLLOCK
I
OUTA
OR I
OUTB
DATA
t
LPW
t
D
t
PD
t
PD
DATA ENTERS INPUT
LATCHES ON THIS EDGE
Figure 12. Internal Timing of AD9772A with PLL Disabled
Figure 13 illustrates the details of the RESET function timing.
RESET going from a high to a low logic level enables the 1
clock output, generated by the PLLLOCK pin. If RESET goes
low at a time well before the rising edge of the 2 clock, then
PLLLOCK will go high on the following edge of the 2 clock. If
RESET goes from a high to a low logic level 600 ps or later
following the rising edge of the 2
×
clock, there will be a delay of
one 2 clock cycle before PLLLOCK goes high. In either case,
as long as RESET remains low, PLLLOCK will change state on
every rising edge of the 2 clock. As stated before, it is the rising
edge of the 2 clock which immediately precedes the rising edge
of PLLLOCK that latches data into the AD9772A input latches.
CH1 2.00V CH2 2.00V M 10.0ns CH3 2.00V
.
[ T ]
1
2
3
T
T
T
CH1 2.00V CH2 2.00V M 10.0ns CH4 1.20V
CH3 2.00V
b.
Figure 13. RESET Timing of AD9772A with PLL Disabled
a.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9772AASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP T/R |
| AD9772AASTZ | 功能描述:IC DAC 14BIT 160MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9772AASTZRL | 功能描述:IC DAC 14BIT 160MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9772A-EB | 制造商:Analog Devices 功能描述:14 BIT DAC W/2X INTERPOLATION 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9772A - Bulk |
| AD9772A-EBZ | 功能描述:BOARD EVAL FOR AD9772A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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