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| 型號(hào)： | AD9772AAST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 14-BIT DAC, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 596K |
| 代理商： | AD9772AAST |
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REV. A
AD9772A
–13–
“Zero Stuffing” Option Description
As shown in Figure 7, a
“
zero
”
or null in the frequency responses
(after interpolation and DAC reconstruction) occurs at the final
DAC update rate (i.e., 2
f
DATA
) due to the DAC
’
s inherent
sin(x)/x roll-off response. In baseband applications, this roll-off
in the frequency response may not be as problematic since much
of the desired signal energy remains below f
DATA
/2 and the
amplitude variation is not as severe. However, in direct IF
applications interested in extracting an image above f
DATA
/2,
this roll-off may be problematic due to the increased passband
amplitude variation as well as the reduced signal level of the
higher images.
FREQUENCY
–
f
DATA
0
–
10
–
40
0
4
0.5
1
1.5
2
2.5
3
3.5
–
20
–
30
WITH
“
ZERO-STUFFING
”
WITHOUT
“
ZERO-STUFFING
”
BASEBAND
REGION
d
Figure 7. Effects of “Zero-Stuffing” on DAC’s
Sin(x)/x Response
For instance, if the digital data into the AD9772A represented a
baseband signal centered around f
DATA
/4 with a passband of
f
DATA
/10, the reconstructed baseband signal out of the AD9772A
would experience only a 0.18 dB amplitude variation over its
passband with the
“
first image
”
occurring at 7/4 f
DATA
with 17 dB
of attenuation relative to the fundamental. However, if the high-
pass filter response was selected, the AD9772A would now
produce pairs of images at [(2N + 1)
= 0, 1 . . .. Note, due to the DAC
’
s sin(x)/x response, only the
lower or upper sideband images centered around f
DATA
may
be useful although they would be attenuated by
–
2.1 dB and
–
6.54 dB respectively, as well as experience a passband amplitude
roll-off of 0.6 dB and 1.3 dB.
To improve upon the passband flatness of the desired image
and/or to extract higher images (i.e., 3
the
“
zero-stuffing
”
option should be employed by bringing the
MOD1 pin HIGH. This option increases the effective DAC
update rate by another
factor of two
since a
“
midscale
”
sample
(i.e., 10 0000 0000 0000) is inserted after every data sample
originating from the 2
interpolation filter. A digital multiplexer
switching at a rate of 4
f
DATA
between the interpolation filter
’
s
output and a data register containing the
“
midscale
”
data sample is
used to implement this option as shown in Figure 6. Hence, the
DAC output is now forced to return to its differential midscale
current value (i.e., I
OUTA
–
I
OUTB
0 mA) after reconstructing
each data sample from the digital filter.
The net effect is to increase the DAC update rate such that the
“
zero
”
in the sin(x)/x frequency response now occurs at 4
along with a corresponding reduction in output power as shown
f
DATA
]
±
f
DATA
/4 where N
f
DATA
±
f
FUNDAMENTAL
)
f
DATA
in Figure 7. Note that if the 2 interpolation filter
’
s high-pass
response is also selected, this action can be modeled as a
“
1/4
wave
”
digital mixing process since this is equivalent to digitally
mixing the impulse response of the low-pass filter with a square
wave having a frequency of exactly f
DATA
(i.e., f
DAC
/4).
It is important to realize that the
“
zero stuffing
”
option by itself
does not change the location of the images but rather their signal
level, amplitude flatness and relative weighting. For instance, in
the previous example, the passband amplitude flatness of the
lower and upper sideband images centered around f
DATA
are
improved to 0.14 dB and 0.24 dB respectively, while the signal
level has changed to
–
6.5 dBFS and
–
7.5 dBFS. The lower or
upper sideband image centered around 3
amplitude flatness of 0.77 dB and 1.29 dB with signal levels of
approximately
–
14.3 dBFS and
–
19.2 dBFS.
f
DATA
will exhibit an
PLL CLOCK MULTIPLIER OPERATION
The Phase Lock Loop (PLL) clock multiplier circuitry along
with the clock distribution circuitry can produce the necessary
internally synchronized 1 , 2 , and 4 clocks for the edge
triggered latches, 2
interpolation filter,
“
zero stuffing
”
multi-
plier, and DAC. Figure 8 shows a functional block diagram of
the PLL clock multiplier, which consists of a phase detector, a
charge pump, a voltage controlled oscillator (VCO), a prescaler,
and digital control inputs/outputs. The clock distribution
circuitry generates all the internal clocks for a given mode of
operation. The charge pump and VCO are powered from
PLLVDD while the differential clock input buffer, phase detector,
prescaler and clock distribution circuitry are powered from
CLKVDD. To ensure optimum phase noise performance from
the PLL clock multiplier and clock distribution circuitry,
PLLVDD and CLKVDD must originate from the same clean
analog supply.
CHARGE
PUMP
PHASE
DETECTOR
EXT/INT
CLOCK CONTROL
PRESCALER
CLKVDD
OUT1
CLKCOM
M
M
R
CLK+
LPF
PLL
VDD
DNC
2.7V TO
3.6V
PLL
COM
D
D
CLOCK
DISTRIBUTION
–
+
PLLLOCK
CLK
–
VCO
AD9772A
Figure 8. Clock Multiplier with PLL Clock
Multiplier Enabled
The PLL clock multiplier has two modes of operation. It can be
enabled for less demanding applications providing a reference
clock meeting the minimum specified input data rate of 6MSPS.
It can be disabled for applications below this data rate or for
applications requiring higher phase noise performance. In this
case, a reference clock at
twice
the input data rate (i.e., 2
must be provided
without
the
“
zero stuffing
”
option selected
and
four times
the input data rate (i.e., 4
“
zero stuffing
”
option selected. Note, multiple AD9772A devices
f
DATA
)
f
DATA
)
with
the
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9772AASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP T/R |
| AD9772AASTZ | 功能描述:IC DAC 14BIT 160MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9772AASTZRL | 功能描述:IC DAC 14BIT 160MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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