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參數(shù)資料
| 型號： | AD974 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 4-Channel, 16-Bit, 200 kSPS Data Acquisition System |
| 中文描述： | 4通道，16位，200 kSPS的數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 202K |
| 代理商： | AD974 |
REV. A
–3–
AD974
A Grade
Min
B Grade
Min
Parameter
DIGITAL OUTPUTS
Data Format
Data Coding
V
OL
V
OH
Output Capacitance
Leakage Current
Conditions
Typ
Max
Typ
Max
Units
Serial 16 Bits
Straight Binary
+0.4
I
SINK
= 1.6 mA
I
SOURCE
= 500
μ
A
High-Z State
High-Z State
V
OUT
= 0 V to V
DIG
+0.4
V
V
pF
+4
+4
15
15
±
5
±
5
μ
A
POWER SUPPLIES
Specified Performance
V
DIG
V
ANA
I
DIG
I
Power Dissipation
PWRD LOW
PWRD HIGH
+4.75
+4.75
+5
+5
4.5
14
+5.25
+5.25
+4.75 +5
+4.75 +5
+5.25
+5.25
V
V
mA
mA
4.5
14
120
120
mW
μ
W
50
50
TEMPERATURE RANGE
Specified Performance
T
MIN
to T
MAX
–40
+85
–40
+85
°
C
NOTES
1
LSB means Least Significant Bit. With a
±
10 V input, one LSB is 305
μ
V.
2
Typical rms noise at worst case transitions and temperatures.
3
Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage, and includes the effect
of offset error. For bipolar input, the Full-Scale Error is the worst case of either the –Full-Scale or +Full-Scale code transition voltage errors. For unipolar input
ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage.
4
External 2.5 V reference connected to REF.
5
All specifications in dB are referred to a full-scale
±
10 V input.
6
Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB, or 10 bits of accuracy.
7
Recovers to specified performance after a 2
×
FS input overvoltage.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(f
S
= 200 kHz, V
DIG
= V
ANA
= +5 V, –40
8
C to +85
8
C)
Parameter
Convert Pulsewidth
R/
C
,
CS
to
BUSY
Delay
BUSY
LOW Time
BUSY
Delay after End of Conversion
Aperture Delay
Conversion Time
Acquisition Time
Throughput Time
R/
C
Low to DATACLK Delay
DATACLK Period
DATA Valid Setup Time
DATA Valid Hold Time
EXT. DATACLK Period
EXT. DATACLK HIGH
EXT. DATACLK LOW
R/
C
,
CS
to EXT. DATACLK Setup Time
R/
C
to
CS
Setup Time
EXT. DATACLK to SYNC Delay
EXT. DATACLK to DATA Valid Delay
CS
to EXT. DATACLK Rising Edge Delay
Previous DATA Valid after
CS
, R/
C
Low
BUSY
to EXT. DATACLK Setup Time
Final EXT. DATACLK to
BUSY
Rising Edge
A0, A1 to
WR1
,
WR2
Setup Time
A0, A1 to
WR1
,
WR2
Hold Time
WR1
,
WR2
Pulsewidth
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
6
+ t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
Min
50
Typ
Max
Units
ns
ns
μ
s
ns
ns
μ
s
μ
s
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
ns
μ
s
ns
ns
ns
100
4.0
50
40
3.8
4.0
1.0
5
220
220
50
20
66
20
30
20
10
15
25
10
3.5
5
t
12
+ 5
66
66
1.7
10
10
50
Specifications subject to change without notic e.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD974AN | 4-Channel, 16-Bit, 200 kSPS Data Acquisition System |
| AD974AR | 4-Channel, 16-Bit, 200 kSPS Data Acquisition System |
| AD974BN | 4-Channel, 16-Bit, 200 kSPS Data Acquisition System |
| AD974BR | 4-Channel, 16-Bit, 200 kSPS Data Acquisition System |
| AD974BRS | 4-Channel, 16-Bit, 200 kSPS Data Acquisition System |
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