參數(shù)資料
型號： AD9633BCPZRL7-105
廠商： Analog Devices Inc
文件頁數(shù)： 32/40頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL 105MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 105M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 473mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個差分，雙極
AD9633
Data Sheet
Rev. 0 | Page 38 of 40
Table 19. Input Clock Phase Adjust Options
Input Clock Phase
Adjust, Bits[6:4]
Number of Input Clock Cycles of
Phase Delay
000 (Default)
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Bits[3:0]—Output Clock Phase Adjust
Table 20. Output Clock Phase Adjust Options
Output Clock (DCO),
Phase Adjust, Bits[3:0]
DCO Phase Adjustment (Degrees
Relative to D0±x/D1±x Edge)
0000
0
0001
60
0010
120
0011 (Default)
180
0100
240
0101
300
0110
360
0111
420
1000
480
1001
540
1010
600
1011
660
Serial Output Data Control (Register 0x21)
The serial output data control register is used to program the
AD9633 in various output data modes depending upon the data
capture solution. Table 21 describes the various serialization
options available in the AD9633.
Resolution/Sample Rate Override (Register 0x100)
This register is designed to allow the user to downgrade the device.
Any attempt to upgrade the default speed grade results in a chip
power-down. Settings in this register are not initialized until Bit 0
of the transfer register (Register 0xFF) is written high.
User I/O Control 2 (Register 0x101)
Bits[7:1]—Open
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM
generator. This feature is used when applying an external
reference.
Bits[2:0]—Open
Table 21. SPI Register Options
Serialization Options Selected
Register 0x21
Contents
Serial Output Number
of Bits (SONB)
Frame Mode
Serial Data Mode
DCO Multiplier
Timing Diagram
0x32
12-bit
1×
DDR two-lane bytewise
3 × fS
Figure 2 (default setting)
0x22
12-bit
1×
DDR two-lane bitwise
3 × fS
0x12
12-bit
1×
SDR two-lane bytewise
6 × fS
0x02
12-bit
1×
SDR two-lane bitwise
6 × fS
0x36
12-bit
2×
DDR two-lane bytewise
3 × fS
0x26
12-bit
2×
DDR two-lane bitwise
3 × fS
0x16
12-bit
2×
SDR two-lane bytewise
6 × fS
0x06
12-bit
2×
SDR two-lane bitwise
6 × fS
0x42
12-bit
1×
DDR one-lane
6 × fS
0x33
10-bit
1×
DDR two-lane bytewise
2.5 × fS
0x23
10-bit
1×
DDR two-lane bitwise
2.5 × fS
0x13
10-bit
1×
SDR two-lane bytewise
5 × fS
0x03
10-bit
1×
SDR two-lane bitwise
5 × fS
0x37
10-bit
2×
DDR two-lane bytewise
2.5 × fS
0x27
10-bit
2×
DDR two-lane bitwise
2.5 × fS
0x17
10-bit
2×
SDR two-lane bytewise
5 × fS
0x07
10-bit
2×
SDR two-lane bitwise
5 × fS
0x43
10-bit
1×
DDR one-lane
5 × fS
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AD9633BCPZRL7-80 功能描述:IC ADC 12BIT SRL 80MSPS 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極
AD9634 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170 MSPS/210 MSPS/250 MSPS
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AD9634-210EBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 12 Bit 210 Msps ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
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