參數(shù)資料
型號(hào)： AD9633BCPZRL7-105
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 20/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL 105MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 105M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 473mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 4 個(gè)差分，雙極
Data Sheet
AD9633
Rev. 0 | Page 27 of 40
DIGITAL OUTPUTS AND TIMING
The AD9633 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SPI. The LVDS driver current is derived on chip and sets the
output current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing (or 700 mV p-p
differential) at the receiver.
When operating in reduced range mode, the output current is
reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-
p differential) across a 100 Ω termination at the receiver.
The AD9633 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be less than 24 inches and
that the differential output traces be close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position is shown in Figure 69. Figure 70 shows
the LVDS output timing example in reduced range mode.
10
07
3-
07
4
D0 500mV/DIV
D1 500mV/DIV
DCO 500mV/DIV
FCO 500mV/DIV
4ns/DIV
Figure 69. AD9633-125, LVDS Output Timing Example in ANSI-644 Mode
(Default)
100
73
-083
D0 400mV/DIV
D1 400mV/DIV
DCO 400mV/DIV
FCO 400mV/DIV
4ns/DIV
Figure 70. AD9633-125, LVDS Output Timing Example in Reduced Range Mode
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on standard FR-4 material is
shown in Figure 71.
5.5k
4.5k
5.0k
4.0k
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
0
350ps
400ps
500ps
450ps
550ps
600ps
650ps
700ps
TI
E
J
ITTE
R
H
IS
T
OGR
A
M
(H
it
s
)
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns
–0.5ns
0ns
0.5ns
1.0ns
E
YE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V
)
EYE: ALL BITS
ULS: 8000/300062
1007
3-
075
Figure 71. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End
Termination Only
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9633BCPZRL7-125 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12 bit 125msps low pwr quad ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類(lèi)型: 信噪比: 接口類(lèi)型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
AD9633BCPZRL7-80 功能描述:IC ADC 12BIT SRL 80MSPS 48LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類(lèi)型:1 個(gè)單端，雙極
AD9634 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:12-Bit, 170 MSPS/210 MSPS/250 MSPS
AD9634-170EBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 12 Bit 170 Msps ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V
AD9634-210EBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 12 Bit 210 Msps ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V
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