參數(shù)資料
型號: AD9637BCPZRL7-80
廠商: Analog Devices Inc
文件頁數(shù): 1/40頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SRL 80MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 12
采樣率(每秒): 80M
數(shù)據(jù)接口: LVDS,串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 574mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: *
輸入數(shù)目和類型: 8 個(gè)差分
Octal, 12-Bit, 40/80 MSPS, Serial LVDS,
1.8 V Analog-to-Digital Converter
Data Sheet
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2011–2013 Analog Devices, Inc. All rights reserved.
FEATURES
Low power: 60 mW per channel at 80 MSPS with scalable
power options
SNR = 71.5 dBFS (to Nyquist)
SFDR = 92 dBc (to Nyquist)
DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p differential input voltage range
1.8 V supply operation
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 80 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
FUNCTIONAL BLOCK DIAGRAM
ADC
12
SERIAL
LVDS
D+ A
D– A
VIN+ A
AVDD
AD9637
VIN– A
ADC
12
SERIAL
LVDS
D+ B
D– B
VIN+ B
VIN– B
ADC
12
SERIAL
LVDS
D+ C
D– C
VIN+ C
VIN– C
ADC
12
SERIAL
LVDS
D+ D
D– D
VIN+ D
VIN– D
ADC
12
SERIAL
LVDS
D+ E
D– E
VIN+ E
VIN– E
ADC
12
SERIAL
LVDS
D+ F
D– F
VIN+ F
VIN– F
ADC
12
SERIAL
LVDS
D+ G
D– G
VIN+ G
VIN– G
ADC
12
SERIAL
LVDS
DATA
RATE
MULTIPLIER
SERIAL PORT
INTERFACE
REF
SELECT
D+ H
FCO+
FCO–
DCO+
DCO–
D– H
VIN+ H
VIN– H
VREF
VCM
1.0V
SYNC
SENSE
PDWN
DRVDD
RBIAS
AGND
CSB
CLK+ CLK–
SDIO/
DFS
SCLK/
DTP
10
215
-0
01
Figure 1.
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is
specified over the industrial temperature range of 40°C to +85°C.
This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
Small Footprint. Eight ADCs are contained in a small,
space-saving package.
2.
Low Power of 60 mW/Channel at 80 MSPS with Scalable
Power Options.
3.
Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 480 MHz and supports
double data rate (DDR) operation.
4.
User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
5.
Pin Compatible with the AD9257 (14-Bit Octal ADC).
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