參數(shù)資料
型號(hào)： AD962711-105EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 39/72頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION AD9627 105MSPS
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 11
采樣率（每秒）： 105M
數(shù)據(jù)接口： 串行
輸入范圍： 1 ~ 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 600mW @ 105MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD962711
已供物品： 板
AD9627-11
Rev. B | Page 44 of 72
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x117
Signal Monitor
Result
Channel A
Register 1
(Global)
Signal Monitor Result Channel A[15:8]
Read only
0x118
Signal Monitor
Result
Channel A
Register 2
(Global)
Open
Signal Monitor Value Channel A[19:16]
Read only
0x119
Signal Monitor
Result
Channel B
Register 0
(Global)
Signal Monitor Result Channel B[7:0]
Read only
0x11A
Signal Monitor
Result
Channel B
Register 1
(Global)
Signal Monitor Result Channel B[15:8]
Read only
0x11B
Signal Monitor
Result
Channel B
Register 2
(Global)
Open
Signal Monitor Result Channel B[19:16]
Read only
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see Application Note AN-877,
Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bit 7—Signal Monitor Sync Enable
Bit 7 enables the sync pulse from the external SYNC input to
the signal monitor block. The sync signal is passed when Bit 7
and Bit 0 are high. This is continuous sync mode.
Bits[6:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the clock
divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2
allows the clock divider to sync to the first sync pulse it receives
and to ignore the rest. The clock divider sync enable bit
(Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
passed when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
Fast Detect Control (Register 0x104)
Bits[7:4]—Reserved
Bits[3:1]—Fast Detect Mode Select
These bits set the mode of the fast detect output pins (see Table 14).
Bit 0—Fast Detect Enable
Bit 0 is used to enable the fast detect output pins. When the
fast detect output pins are disabled, the outputs go into a high
impedance state. In LVDS mode, when the outputs are inter-
leaved, the outputs go high-Z only if both channels are turned
off (power-down/standby/output disabled). If only one channel is
turned off (power-down/standby/output disabled), the fast detect
output pins repeat the data of the active channel.
Coarse Upper Threshold (Register 0x105)
Bits[7:3]—Reserved
Bits[2:0]—Coarse Upper Threshold
These bits set the level required to assert the coarse upper
threshold indication (see Table 18).
Fine Upper Threshold (Register 0x106 and Register 0x107)
Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0]
Register 0x107, Bits[7:5]—Reserved
Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8]
These registers provide the fine upper limit threshold. This 13-bit
value is compared to the 13-bit magnitude from the ADC block.
If the ADC magnitude exceeds this threshold value, the F_UT
flag is set.
Fine Lower Threshold (Register 0x108 and Register 0x109)
Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0]
Register 0x109, Bits[7:5]—Reserved
Register 0x109, Bits[4:0]—Fine Lower Threshold[12:8]
These registers provide the fine lower limit threshold. This 13-bit
value is compared to the 13-bit magnitude from the ADC block.
If the ADC magnitude is less than this threshold value, the F_LT
flag is set.
OBSOLETE
相關(guān)PDF資料
PDF描述
UPB2D561MRD CAP ALUM 560UF 200V 20% RADIAL
AD9609-80EBZ BOARD EVALUATION AD9609 80MSPS
AD9629-40EBZ BOARD EVALUATION AD9629 40MSPS
STD21W-K WIRE & CABLE MARKERS
UPB2C681MRD CAP ALUM 680UF 160V 20% RADIAL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9627-125EBZ 功能描述:IC A/D 12BIT 125MSPS DL EVAL BRD RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
AD9627-150EBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 12Bit 150 Msps Dual 1.8V PB Free ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
AD9627ABCPZ-105 功能描述:IC ADC 12BIT 105MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
AD9627ABCPZ11-105 功能描述:IC ADC 11BIT 105MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
AD9627ABCPZ11-150 功能描述:IC ADC 11BIT 150MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*