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參數(shù)資料
| 型號： | AD962711-105EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/72頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION AD9627 105MSPS |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 1 ~ 2 Vpp |
| 在以下條件下的電源（標準）： | 600mW @ 105MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD962711 |
| 已供物品： | 板 |
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AD9627-11
Rev. B | Page 26 of 72
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 54 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
2.5
–2.5
–40
TEMPERATURE (°C)
R
E
F
E
RE
NC
E
V
O
L
T
AG
E
RRO
R
(
m
V
)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–20
0
204060
80
07
05
4-
05
4
Figure 54. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 15). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9627-11 sample clock inputs,
CLK+ and CLK, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
(see Figure 55) and require no external bias.
1.2V
AVDD
2pF
CLK–
CLK+
0
70
54-
0
55
Figure 55. Equivalent Clock Input Circuit
Clock Input Options
The AD9627-11 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
section.
Figure 56 and Figure 57 show two preferred methods for clocking
the AD9627-11 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock
frequencies between 125 MHz and 625 MHz, and the RF
transformer is recommended for clock frequencies from 10 MHz
to 200 MHz. The back-to-back Schottky diodes across the
transformer/balun secondary limit clock excursions into the
AD9627-11 to approximately 0.8 V p-p differential.
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9627-11 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
Mini-Circuits
ADT1–1WT, 1:1Z
XFMR
CLK–
CLK+
ADC
AD9627-11
070
54
-05
6
Figure 56. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1F
1nF
CLOCK
INPUT
1nF
50
SCHOTTKY
DIODES:
HSMS2822
CLK–
CLK+
ADC
AD9627-11
07
05
4-
0
57
Figure 57. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
jitter performance.
100
0.1F
240
240
PECL DRIVER
50k
50k
CLOCK
INPUT
CLOCK
INPUT
AD951x
CLK–
CLK+
ADC
AD9627-11
07054-
058
Figure 58. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 59. The AD9510/
drivers offer excellent jitter performance.
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