- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16521 > AD9547/PCBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9547 PDF資料下載
參數(shù)資料
| 型號： | AD9547/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9547 |
| 設(shè)計資源： | AD9547 Schematic AD9574 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9547 |
| 主要屬性： | 2 個差分式或 4 個單端輸入 |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
AD9547
Data Sheet
Rev. E | Page 16 of 104
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
20
I
Differential
input
CLKINN
Clock DistributionInput. In standard operating mode, this pin is connected to
the filteredDACOUTNoutput.Thisinternally biasedinputis typically ac-coupled,
and, when configured as such, can accept any differential signal with a single-
ended swing of at least 400 mV.
21
I
Differential
input
CLKINP
Clock DistributionInput. In standard operating mode, this pin is connected to
the filteredDACOUTP output.
23
I
Power
AVDD
1.8 V Analog (Input Receiver) Power Supply.
24
O
Current set
resistor
OUT_RSET
Connect an optional 3.12 k resistor from this pin to ground (see the Output
25, 31
I
Power
AVDD3
Analog Supply for Output Driver. These pins are normally 3.3 V but can be
1.8 V. Pin 25 powers OUT0. Pin 31 powers OUT1. Apply power to these pins
even if the corresponding outputs (OUT0P/OUT0N, OUT1P/OUT1N) are not
used. See the Power Supply Partitions section.
26
O
LVPECL,
LVDS, or
CMOS
OUT0P
Output 0. This output can be configured as LVPECL, LVDS, or single-ended
CMOS. LVPECL and LVDS operationrequire a 3.3 V output driver power
supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output
driver power supply.
27
O
LVPECL,
LVDS, or
CMOS
OUT0N
Complementary Output 0. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
28, 32
I
Power
AVDD
1.8 V Analog (Output Divider) Power Supply.
29
O
LVPECL,
LVDS, or
CMOS
OUT1P
Output 1. This output can be configured as LVPECL, LVDS, or single-ended
CMOS. LVPECL and LVDS operationrequire a 3.3 V output driver power
supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output
driver power supply.
30
O
LVPECL,
LVDS, or
CMOS
OUT1N
Complementary Output 1. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
33
I
Power
AVDD3
3.3 V Analog (System Clock) Power Supply.
34
I
SYSCLK_VREG
System Clock Loop Filter Voltage Regulator. Connect a 0.1 μF capacitor from
this pinto ground. This pinis also the ac ground reference for the integrated
externalloopfilter ofthe SYSCLK PLL multiplier(seethe SYSCLK PLL Multiplier
section).
35
O
SYSCLK_LF
System Clock Multiplier Loop Filter. Whenusing the frequency multiplier to
drive the system clock, an external loop filter can be attached to this pin.
36, 39
I
Power
AVDD
1.8 V Analog (System Clock) Power Supply.
37
I
Differential
input
SYSCLKN
Complementary System Clock Input. Complementary signal to SYSCLKP.
SYSCLKN containsinternaldc biasingandshouldbe ac-coupledwitha 0.01μF
capacitor, except when using a crystal. When using a crystal, connect it across
SYSCLKP and SYSCLKN.
38
I
Differential
input
SYSCLKP
System Clock Input. SYSCLKP contains internal dc biasing and should be ac-
coupledwith a 0.01 μF capacitor, except when using a crystal. When using a
crystal, connect it directly across SYSCLKP and SYSCLKN. Single-ended 1.8 V
CMOS is also an option but can introduce a spur if the doubler is enabledand
the duty cycle is not 50%. When using SYSCLKP as a single-ended input,
connect a 0.01 μF capacitor from SYSCLKN to ground.
40, 41
I
TDC_VRB,
TDC_VRT
Use capacitive decouplingon these pins (see Figure 37).
42
I
Power
AVDD
1.8 V Analog (Time-to-Digital Converter) Power Supply.
43, 49
I
Power
AVDD3
3.3 V Analog (Reference Input) Power Supply.
44
I
Differential
input
REFA
Reference A Input. This internally biased input is typically ac-coupledand,
when configured as such, can accept any differential signal with a single-
endedswingofup to 3.3 V. Ifdc-coupled,input canbeLVPECL, CMOS,or LVDS.
45
I
Differential
input
REFAA
Complementary Reference A Input. Complementary signal to the input pro-
videdonPin44. The usercanconfigurethis pinas a separatesingle-endedinput.
46, 50
I
Power
AVDD
1.8 V Analog (Reference Input) Power Supply.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPA1E331MPD1TD | CAP ALUM 330UF 25V 20% RADIAL |
| LB2518T331M | INDUCTOR WOUND 330UH 30MA 1007 |
| VI-J0T-EZ-S | CONVERTER MOD DC/DC 6.5V 25W |
| AD9540/PCBZ | BOARD EVAL CLK GEN SYNTH 48LFCSP |
| HCM15DSEH-S243 | CONN EDGECARD 30POS .156 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9548 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer |
| AD9548/PCBZ | 功能描述:BOARD EVAL FOR AD9548 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9548/PCBZ | 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board |
| AD9548BCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| AD9548BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。