參數(shù)資料
型號(hào)： AD9524/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 47/56頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9524
設(shè)計(jì)資源： AD9524 Schematic
AD9524 BOM
AD9524 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9524
主要屬性： USB 供電或外部電源
次要屬性： 狀態(tài) LED
已供物品： 板
配用： AD9524BCPZ-ND - IC INTEGER-N CLCK GEN 48LFCSP
Data Sheet
AD9524
Rev. E | Page 51 of 56
Address
Bits
Bit Name
Description
1
Tristate output
0x197
[7:0]
Channel divider, Bits[7:0] (LSB)
Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0] = 1
is divided by 2 … [9:0] = 1023 is divided by 1024. 10-bit channel divider, Bits[7:0] (LSB).
0x198
[7:2]
Divider phase
Divider initial phase after a sync is asserted relative to the divider input clock (from the
VCO divider output). LSB = of a period of the divider input clock.
Phase = 0: no phase offset.
Phase = 1: period offset, …
Phase = 63: 31 period offset.
[1:0]
Channel divider, Bits[9:8] (MSB)
10-bit channel divider, Bits[9:8] (MSB).
Table 53. PLL1 Output Control (PLL1_OUT, Pin 46)
Address
Bits
Bit Name
Description
0x1BA
[7:5]
Reserved
4
PLL1 output CMOS driver
strength
CMOS driver strength
1: weak
0: strong
[3:0]
PLL1 output divider
0000: divide-by-1
0001: divide-by-2 (default)
0010: divide-by-4
0100: divide-by-8
1000: divide-by-16
No other inputs permitted
Table 54. PLL1 Output Channel Control
Address
Bits
Bit Name
Description
0x1BB
7
PLL1 output driver power-down
[6:2]
Reserved
1
Route VCXO clock to
Channel 1 divider input
1: channel uses VCXO clock. Routes VCXO clock to divider input
0: channel uses VCO divider output clock
0
Route VCXO clock to
Channel 0 divider input
1: channel uses VCXO clock. Routes VCXO clock to divider input
0: channel uses VCO divider output clock
Readback (Address 0x22C to Address 0x22D)
Table 55. Readback Registers (Readback 0 and Readback 1)
Address
Bits
Bit Name
Description
0x22C
7
Status PLL2 reference clock
1: OK
0: off/clocks are missing
6
Status PLL1 feedback clock
1: OK
0: off/clocks are missing
5
Status VCXO
1: OK
0: off/clocks are missing
4
Status REF_TEST
1: OK
0: off/clocks are missing
3
Status REFB
1: OK
0: off/clocks are missing
2
Status REFA
1: OK
0: off/clocks are missing
1
Lock detect PLL2
1: locked
0: unlocked
0
Lock detect PLL1
1: locked
0: unlocked
相關(guān)PDF資料
PDF描述
V150C12E150BF CONVERTER MOD DC/DC 12V 150W
0982660986 CBL 27PS 0.5MM JMPR TYPE D 1.18"
H6MMH-3006G DIP CABLE - HDM30H/AE30G/HDM30H
TCMD-25-T-02.00-01-N CABLE ASSEM 2MM 50POS M-F 2"
GEC17DRXI-S734 CONN EDGECARD 34POS DIP .100 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9525 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Jitter Clock Generator with Eight LVPECL Outputs
AD9525/PCBZ 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Evaluation kit 2950MHz VCO installed RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9525/PCBZ-VCO 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Evaluation kit CRO29508 VCO installed RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9525BCPZ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 High performance clock distributor Exter RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9525BCPZ-REEL7 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 High performance clock distributor Exter RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*