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參數(shù)資料
| 型號： | AD9524/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9524 |
| 設計資源： | AD9524 Schematic AD9524 BOM AD9524 Gerber Files |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9524 |
| 主要屬性： | USB 供電或外部電源 |
| 次要屬性： | 狀態(tài) LED |
| 已供物品： | 板 |
| 配用： | AD9524BCPZ-ND - IC INTEGER-N CLCK GEN 48LFCSP |
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Data Sheet
AD9524
Rev. E | Page 27 of 56
SERIAL CONTROL PORT
The AD9524 serial control port is a flexible, synchronous serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9524 serial control port is compatible with most synchronous
transfer formats, including Philips I2C, Motorola SPI, and
Intel SSR protocols. The AD9524 I2C implementation deviates
from the classic I2C specification in two specifications, and
these deviations are documented in Table 16 of this data sheet.
The serial control port allows read/write access to all registers
that configure the AD9524.
SPI/IC PORT SELECTION
The AD9524 has two serial interfaces, SPI and I2C. Users can select
either the SPI or I2C, depending on the states (logic high, logic low)
of the two logic level input pins, SP1 and SP0, when power is
applied or after a RESET (each pin has an internal 40 kΩ pull-
down resistor). When both SP1 and SP0 are low, the SPI interface
is active. Otherwise, I2C is active with three different I2C slave
address settings (seven bits wide), as shown in Table 22. The
five MSBs of the slave address are hardware coded as 11000, and
the two LSBs are determined by the logic levels of the SP1 and
SP0 pins.
Table 22. Serial Port Mode Selection
SP1
SP0
Address
Low
SPI
Low
High
I2C: 1100000
High
Low
I2C: 1100001
High
I2C: 1100010
IC SERIAL PORT OPERATION
The AD9524 I2C port is based on the I2C fast mode standard.
The AD9524 supports both I2C protocols: standard mode
(100 kHz) and fast mode (400 kHz).
The AD9524 I2C port has a 2-wire interface consisting of a serial
data line (SDA) and a serial clock line (SCL). In an I2C bus system,
the AD9524 is connected to the serial bus (data bus SDA and clock
bus SCL) as a slave device, meaning that no clock is generated by
the AD9524. The AD9524 uses direct 16-bit (two bytes) memory
addressing instead of traditional 8-bit (one byte) memory
addressing.
I2C Bus Characteristics
Table 23. I2C Bus Definitions
Abbreviation
Definition
S
Start
Sr
Repeated start
P
Stop
A
Acknowledge
A
No acknowledge
W
Write
R
Read
One pulse on the SCL clock line is generated for each data bit
that is transferred.
The data on the SDA line must not change during the high period
of the clock. The state of the data line can change only when the
clock on the SCL line is low.
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
0
9081
-160
Figure 30. Valid Bit Transfer
A start condition is a transition from high to low on the SDA
line while SCL is high. The start condition is always generated
by the master to initialize the data transfer.
A stop condition is a transition from low to high on the SDA
line while SCL is high. The stop condition is always generated
by the master to end the data transfer.
START
CONDITION
S
STOP
CONDITION
P
SDA
SCL
09081-
161
Figure 31. Start and Stop Conditions
A byte on the SDA line is always eight bits long. An acknowledge
bit must follow every byte. Bytes are sent MSB first.
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