參數(shù)資料
型號(hào)： AD9524/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 39/56頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD9524
設(shè)計(jì)資源： AD9524 Schematic
AD9524 BOM
AD9524 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9524
主要屬性： USB 供電或外部電源
次要屬性： 狀態(tài) LED
已供物品： 板
配用： AD9524BCPZ-ND - IC INTEGER-N CLCK GEN 48LFCSP
AD9524
Data Sheet
Rev. E | Page 44 of 56
Input PLL (PLL1) (Address 0x010 to Address 0x01D)
Table 35. PLL1 REFA R Divider Control
Address
Bits
Bit Name
Description
0x010
[7:0]
REFA R divider
10-bit REFA R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
0x011
[1:0]
10-bit REFA R divider, Bits[9:8] (MSB)
Table 36. PLL1 REFB R Divider Control1
Address
Bits
Bit Name
Description
0x012
[7:0]
REFB R divider
10-bit REFB R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
0x013
[1:0]
10-bit REFB R divider, Bits[9:8] (MSB)
1
Requires Register 0x01C, Bit 7 = 1 for division that is independent of REFA division.
Table 37. PLL1 Reference Test Divider
Address
Bits
Bit Name
Description
0x014
[7:6]
Reserved
[5:0]
REF_TEST divider
6-bit reference test divider. Divide-by-1 to divide-by-63.
000000, 000001: divide-by-1.
Table 38. PLL1 Reserved
Address
Bits
Bit Name
Description
0x015
[7:0]
Reserved
Table 39. PLL1 Feedback N Divider Control
Address
Bits
Bit Name
Description
0x016
[7:0]
PLL1 feedback N divider control
(N_PLL1)
10-bit feedback divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
0x017
[1:0]
10-bit feedback divider, Bits[1:0] (MSB)
Table 40. PLL1 Charge Pump Control
Address
Bits
Bit Name
Description
0x018
7
PLL1 charge pump tristate
Tristates the PLL1 charge pump.
[6:0]
PLL1 charge pump control
These bits set the magnitude of the PLL1 charge pump current. Granularity is ~0.5 μA
with a full-scale magnitude of ~63.5 μA.
0x019
[7:5]
Reserved
Reserved.
4
Enable SPI control of antibacklash
pulse width
Controls the functionality of Register 0x019, Bits[3:2].
0 (default): the device automatically controls the antibacklash period to high
(equivalent to Register 0x019, Bits[3:2] = 10)
1: antibacklash period defined by Register 0x019, Bits[3:2].
[3:2]
Antibacklash pulse width control
Controls the PFD antibacklash period.
00 (default): minimum.
01: low.
10: high.
11: maximum.
These bits are ineffective unless Register 0x019, Bit 4 = 1.
[1:0]
PLL1 charge pump mode
Controls the mode of the PLL1 charge pump.
00: (default) tristate.
01: pump up.
10: pump down.
11: normal.
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