參數(shù)資料
型號(hào)： AD9524/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 46/56頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9524
設(shè)計(jì)資源： AD9524 Schematic
AD9524 BOM
AD9524 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9524
主要屬性： USB 供電或外部電源
次要屬性： 狀態(tài) LED
已供物品： 板
配用： AD9524BCPZ-ND - IC INTEGER-N CLCK GEN 48LFCSP
AD9524
Data Sheet
Rev. E | Page 50 of 56
Reserved (Address 0x190)
Table 51. Reserved Register
Address
Bits
Bit Name
Description
0x190
[7:5]
Reserved
Reserved. The default value for this register is 0x00. It is recommended to write a value
of 0x20 to this register.
Clock Distribution (Address 0x196 to Address 0x1A1, Address 0x1AE to Address 0x1B3, Address 0x1BA, and Address
0x1BB)
Table 52. Channel 0 to Channel 5 Control (This same map applies to all six channels.)
Address
Bits
Bit Name
Description
0x196
7
Invert divider output
Inverts the polarity of the divider’s output clock.
6
Ignore sync
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Power-down channel
1: powers down the entire channel.
0: normal operation.
4
Lower power mode
(differential modes only)
Reduces power used in the differential output modes (LVDS/LVPECL/HSTL). This
reduction may result in power savings, but at the expense of performance. Note that
this bit does not affect output swing and current, just the internal driver power.
1: low strength/lower power.
0: normal operation.
[3:0]
Driver mode
Driver mode.
Bit 3
Bit 2
Bit 1
Bit 0
Driver Mode
0
Tristate output
0
1
LVPECL (8 mA)
0
1
0
LVDS (3.5 mA)
0
1
LVDS (7 mA)
0
1
0
HSTL-0 (16 mA)
0
1
0
1
HSTL-1 (8 mA)
0
1
0
CMOS (both outputs in phase)
+ Pin: true phase relative to divider output
Pin: true phase relative to divider output
0
1
CMOS (opposite phases on outputs)
+ Pin: true phase relative to divider output
Pin: complement phase relative to divider output
1
0
CMOS
+ Pin: true phase relative to divider output
Pin: high-Z
1
0
1
CMOS
+ Pin: high-Z
Pin: true phase relative to divider output
1
0
1
0
CMOS
+ Pin: high-Z
Pin: high-Z
1
0
1
CMOS (both outputs in phase)
+ Pin: complement phase relative to divider output
Pin: complement phase relative to divider output
1
0
CMOS (both outputs out of phase)
+ Pin: complement phase relative to divider output
Pin: true phase relative to divider output
1
0
1
CMOS
+ Pin: complement phase relative to divider output
Pin: high-Z
1
0
CMOS
+ Pin: high-Z
Pin: complement phase relative to divider output
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9525 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Jitter Clock Generator with Eight LVPECL Outputs
AD9525/PCBZ 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Evaluation kit 2950MHz VCO installed RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9525/PCBZ-VCO 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Evaluation kit CRO29508 VCO installed RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9525BCPZ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 High performance clock distributor Exter RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9525BCPZ-REEL7 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 High performance clock distributor Exter RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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