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參數(shù)資料
| 型號： | AD9524/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9524 |
| 設(shè)計資源： | AD9524 Schematic AD9524 BOM AD9524 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9524 |
| 主要屬性： | USB 供電或外部電源 |
| 次要屬性： | 狀態(tài) LED |
| 已供物品： | 板 |
| 配用： | AD9524BCPZ-ND - IC INTEGER-N CLCK GEN 48LFCSP |
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AD9524
Data Sheet
Rev. E | Page 26 of 56
RESET MODES
The AD9524 has a power-on reset (POR) and several other ways to
apply a reset condition to the chip.
Power-On Reset
During chip power-up, a power-on reset pulse is issued when
3.3 V supply reaches ~2.6 V (<2.8 V) and restores the chip
either to the setting stored in EEPROM (EEPROM pin = 1) or
to the on-chip setting (EEPROM pin = 0). At power-on, the
AD9524 executes a SYNC operation, which brings the outputs
into phase alignment according to the default settings. The
output drivers are held in sync for the duration of the internally
generated power-up sync timer (~70 ms). The outputs begin to
toggle after this period.
Reset via the RESET Pin
RESET, a reset (an asynchronous hard reset is executed by briefly
pulling RESET low), restores the chip either to the setting stored in
EEPROM (EEPROM pin = 1) or to the on-chip setting (EEPROM
pin = 0). A reset also executes a sync operation, which brings the
outputs into phase alignment according to the default settings.
When EEPROM is inactive (EEPROM pin = 0), it takes ~2 s for
the outputs to begin toggling after RESET is issued. When
EEPROM is active (EEPROM pin = 1), it takes ~40 ms for the
outputs to toggle after RESET is brought high.
Reset via the Serial Port
The serial port control register allows for a reset by setting Bit 2
and Bit 5 in Register 0x000. When Bit 5 and Bit 2 are set, the
chip enters a reset mode and restores the chip either to the setting
stored in EEPROM (EEPROM pin = 1) or to the on-chip -setting
(EEPROM pin = 0), except for Register 0x000. Except for the self-
clearing bits, Bit 2 and Bit 5, Register 0x000 retains its previous value
prior to reset. During the internal reset, the outputs
hold static. Bit 2
and Bit 5
are self-clearing. However, the self-clearing operation does
not complete until an additional serial port SCLK cycle completes,
and the AD9524 is held in reset until Bit 2 and Bit 5 self clear.
Reset to Settings in EEPROM when EEPROM Pin = 0 via the
Serial Port
The serial port control register allows the chip to be reset to settings
in EEPROM when the EEPROM pin = 1 via Register 0xB02, Bit 1.
This bit is self-clearing. This bit does not have any effect when the
EEPROM pin = 0. It takes ~40 ms for the outputs to begin toggling
after the Soft_EEPROM register is cleared.
POWER-DOWN MODE
Chip Power-Down via PD
Place the AD9524 into a power-down mode by pulling the PD pin
low. Power-down turns off most of the functions and currents
inside the AD9524. The chip remains in this power-down state
until PD is returned to a logic high state. When taken out of power-
down mode, the AD9524 returns to the settings programmed into
its registers prior to the power-down, unless the registers are
changed by new programming while the PD pin is held low.
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