參數(shù)資料
型號(hào): AD9523-1/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 24/60頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9523-1
設(shè)計(jì)資源: AD9523(-1) Eval Board Schematic
AD9523(-1) BOM
AD9523(-1) Gerber Files
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9523
主要屬性: 板載 PLL 環(huán)路濾波器
次要屬性: LED 狀態(tài)指示器
已供物品:
AD9523-1
Rev. B | Page 30 of 60
A repeated start (Sr) condition can be used in place of a stop
condition. Furthermore, a start or stop condition can occur at
any time; partially transferred bytes are discarded.
For an I2C data write transfer containing multiple data bytes,
the peripheral drives a no acknowledge for the data byte that
follows a write to Register 0x234, thereby ending the I2C transfer.
For an I2C data read transfer containing multiple data bytes,
the peripheral drives data bytes of 0x00 for subsequent reads that
follow a read from Register 0x234.
Data Transfer Format
Send byte format. The send byte protocol is used to set up the register address for subsequent commands.
S
Slave Address
W
A
RAM Address High Byte
A
RAM Address Low Byte
A
P
Write byte format. The write byte protocol is used to write a register address to the RAM, starting from the specified RAM address.
S
Slave Address
W
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
Receive byte format. The receive byte protocol is used to read the data byte(s) from the RAM, starting from the current address.
S
Slave Address
R
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
A
P
Read byte format. The combined format of the send byte and the receive byte.
S
Slave
Address
W
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
Sr
Slave
Address
R
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
IC Serial Port Timing
SDA
SCL
S
Sr
P
S
tFALL
tSET; DAT
tLOW
tRISE
tHLD; STR
tHLD; DAT
tHIGH
tFALL
tSET; STR
tHLD; STR
tSPIKE
tSET; STP
tRISE
tIDLE
09278
-1
65
Figure 37. IC Serial Port Timing
Table 23. I2C Timing Definitions
Parameter
Description
fI2C
IC clock frequency
tIDLE
Bus idle time between stop and start conditions
tHLD; STR
Hold time for repeated start condition
tSET; STR
Setup time for repeated start condition
tSET; STP
Setup time for stop condition
tHLD; DAT
Hold time for data
tSET; DAT
Setup time for data
tLOW
Duration of SCL clock low
tHIGH
Duration of SCL clock high
tRISE
SCL/SDA rise time
tFALL
SCL/SDA fall time
tSPIKE
Voltage spike pulse width that must be suppressed by the input filter
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