參數(shù)資料
型號(hào)： AD9523-1/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/60頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9523-1
設(shè)計(jì)資源： AD9523(-1) Eval Board Schematic
AD9523(-1) BOM
AD9523(-1) Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9523
主要屬性： 板載 PLL 環(huán)路濾波器
次要屬性： LED 狀態(tài)指示器
已供物品： 板
AD9523-1
Rev. B | Page 27 of 60
All outputs that are not programmed to ignore the sync are
disabled temporarily while the sync is active. Note that, if
an output is used for the zero delay path, it also disappears
momentarily. However, this is desirable because it ensures
that all the synchronized outputs have a deterministic phase
relationship with respect to the zero delay output and, therefore,
also with respect to the input.
ZERO DELAY OPERATION
Zero delay operation aligns the phase of the output clocks with
the phase of the external PLL reference input. The OUT0 output
is designed to be used as the output for zero delay. There are
two zero delay modes on the AD9523-1: internal and external
(see Figure 31). Note that the external delay mode provides
better matching than the internal delay mode because the
output drivers are included in the zero delay path. Setting the
anitbacklash pulse width control of PLL1 to maximum gives the
best zero delay matching.
Internal Zero Delay Mode
The internal zero delay function of the AD9523-1 is achieved by
feeding the output of Channel Divider 0 back to the PLL1 N
divider. Bit 5 in Register 0x01B is used to select internal zero delay
mode (see Table 41). In the internal zero delay mode, the output
of Channel Divider 0 is routed back to the PLL1 (N divider)
through a mux. PLL1 synchronizes the phase/edge of the output
of Channel Divider 0 with the phase/edge of the reference input.
Because the channel dividers are synchronized to each other,
the outputs of the channel divider are synchronous with the
reference input.
External Zero Delay Mode
The external zero delay function of the AD9523-1 is achieved
by feeding OUT0 back to the ZD_IN input and, ultimately, back
to the PLL1 N divider. In Figure 31, the change in signal routing
for external zero delay is external to the AD9523-1.
Bit 5 in Register 0x01B is used to select the external zero delay
mode. In external zero delay mode, OUT0 must be routed back to
PLL1 (the N divider) through the ZD_IN and ZD_IN pins.
PLL1 synchronizes the phase/edge of the feedback output clock
with the phase/edge of the reference input. Because the channel
dividers are synchronized to each other, the clock outputs are
synchronous with the reference input. Both the reference path
delay and the feedback delay from ZD_IN are designed to have
the same propagation delay from the output drivers and PLL
components to minimize the phase offset between the clock
output and the reference input to achieve zero delay.
INTERNAL FB
ZD_IN
REFA
AD9523-1
FEEDBACK
DELAY
REF
DELAY
ENB
PFD
OUT0
09
278-
02
7
Figure 31. Zero Delay Function
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