參數資料
| 型號： | AD9510BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 51/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIST 8OUT PLL 64LFCSP |
| 標準包裝： | 1 |
| 類型： | 扇出緩沖器（分配），除法器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 配用： | AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510 AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當前第51頁第52頁第53頁第54頁第55頁第56頁
Data Sheet
AD9510
Rev. B | Page 55 of 56
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9510 offers both LVPECL and
LVDS outputs, which are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled, logic (LVPECL)
outputs of the AD9510 provide the lowest jitter clock signals
available from the AD9510. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. A simplified equivalent circuit in Figure 41 shows
the LVPECL output stage.
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 56. The resistor network is
designed to match the transmission line impedance (50 ) and
the desired switching threshold (1.3 V).
Figure 56. LVPECL Far-End Termination
Figure 57. LVPECL with Parallel Transmission Line
LVDS CLOCK DISTRIBUTION
Low voltage differential signaling (LVDS) is a second differential
output option for the AD9510. LVDS uses a current mode
output stage with several user-selectable current levels. The
normal value (default) for this current is 3.5 mA, which yields
350 mV output swing across a 100 resistor. The LVDS outputs
meet or exceed all ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 58.
Figure 58. LVDS Output Termination
Analog-to-Digital Converters, for more information on LVDS.
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits,
the implementation and construction of the PCB is as important as
the circuit design. Proper RF techniques must be used for device
selection, placement, and routing, as well as for power supply
bypassing and grounding to ensure optimum performance.
05046-030
3.3V
LVPECL
50
50
SINGLE-ENDED
(NOT COUPLED)
3.3V
LVPECL
127
127
83
83
VT = VCC – 1.3V
05046-031
3.3V
LVPECL
DIFFERENTIAL
(COUPLED)
3.3V
LVPECL
100
0.1nF
200
200
05046-032
3.3V
LVDS
100
DIFFERENTIAL (COUPLED)
3.3V
LVDS
100
相關PDF資料 |
PDF描述 |
|---|---|
| VI-BWF-MW-B1 | CONVERTER MOD DC/DC 72V 100W |
| AD9520-5BCPZ | IC CLOCK GEN EXT VCO 64-LFCSP |
| M83723/83G1203N | CONN RCPT 3POS WALL MT W/PINS |
| X9116WM8 | IC DIGITAL POT 10K 16TP 8MSOP |
| MS27467E25F35SD | CONN PLUG 128POS STRAIGHT W/SCKT |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9510BCPZ-REEL7 | 功能描述:IC CLOCK DIST 8OUT PLL 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9510-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE, DIVIDER - Bulk 制造商:Analog Devices 功能描述:IC ((NS)) |
| AD9510-VCO/PCBZ | 功能描述:BOARD EVALUATION FOR AD9510 RoHS:是 類別:編程器，開發(fā)系統 >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9511 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9511/PCB | 制造商:Analog Devices 功能描述:1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,DIVIDERS, DELAY ADJUST, FIVE OUTPUTS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。