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參數(shù)資料
| 型號： | AD9510/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 51/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9510 |
| 設(shè)計(jì)資源： | AD9510 Eval Brd BOM AD9510 Eval Brd Schematics AD9510 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時，時鐘分配 |
| 已用 IC / 零件： | AD9510 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9510BCPZ-ND - IC CLOCK DIST 8OUT PLL 64LFCSP AD9510BCPZ-REEL7-ND - IC CLOCK DIST 8OUT PLL 64LFCSP |
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Data Sheet
AD9510
Rev. B | Page 55 of 56
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9510 offers both LVPECL and
LVDS outputs, which are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled, logic (LVPECL)
outputs of the AD9510 provide the lowest jitter clock signals
available from the AD9510. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. A simplified equivalent circuit in Figure 41 shows
the LVPECL output stage.
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 56. The resistor network is
designed to match the transmission line impedance (50 ) and
the desired switching threshold (1.3 V).
Figure 56. LVPECL Far-End Termination
Figure 57. LVPECL with Parallel Transmission Line
LVDS CLOCK DISTRIBUTION
Low voltage differential signaling (LVDS) is a second differential
output option for the AD9510. LVDS uses a current mode
output stage with several user-selectable current levels. The
normal value (default) for this current is 3.5 mA, which yields
350 mV output swing across a 100 resistor. The LVDS outputs
meet or exceed all ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 58.
Figure 58. LVDS Output Termination
Analog-to-Digital Converters, for more information on LVDS.
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits,
the implementation and construction of the PCB is as important as
the circuit design. Proper RF techniques must be used for device
selection, placement, and routing, as well as for power supply
bypassing and grounding to ensure optimum performance.
05046-030
3.3V
LVPECL
50
50
SINGLE-ENDED
(NOT COUPLED)
3.3V
LVPECL
127
127
83
83
VT = VCC – 1.3V
05046-031
3.3V
LVPECL
DIFFERENTIAL
(COUPLED)
3.3V
LVPECL
100
0.1nF
200
200
05046-032
3.3V
LVDS
100
DIFFERENTIAL (COUPLED)
3.3V
LVDS
100
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| AD9510-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE, DIVIDER - Bulk 制造商:Analog Devices 功能描述:IC ((NS)) |
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