參數資料
型號： AD9510/PCBZ
廠商： Analog Devices Inc
文件頁數： 4/56頁
文件大小： 0K
描述： BOARD EVALUATION FOR AD9510
設計資源： AD9510 Eval Brd BOM
AD9510 Eval Brd Schematics
AD9510 Gerber Files
標準包裝： 1
主要目的： 計時，時鐘分配
已用 IC / 零件： AD9510
已供物品： 板
相關產品： AD9510BCPZ-ND - IC CLOCK DIST 8OUT PLL 64LFCSP
AD9510BCPZ-REEL7-ND - IC CLOCK DIST 8OUT PLL 64LFCSP
AD9510
Data Sheet
Rev. B | Page 12 of 56
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLK1 = 400 MHz
395
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT4, OUT7) = 100 MHz
Divide Ratio = 4
All Other LVDS = 50 MHz
Interferer(s)
All LVPECL = 50 MHz
Interferer(s)
CLK1 = 400 MHz
395
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT5, OUT6) = 100 MHz
Divide Ratio = 4
All Other LVDS = 50 MHz
Interferer(s)
All LVPECL = 50 MHz
Interferer(s)
CLK1 = 400 MHz
367
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT4, OUT7) = 100 MHz
Divide Ratio = 4
All Other CMOS = 50 MHz (B Outputs Off)
Interferer(s)
All LVPECL = 50 MHz
Interferer(s)
CLK1 = 400 MHz
367
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT5, OUT6) = 100 MHz
Divide Ratio = 4
All Other CMOS = 50 MHz (B Outputs Off)
Interferer(s)
All LVPECL = 50 MHz
Interferer(s)
CLK1 = 400 MHz
548
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT4, OUT7) = 100 MHz
Divide Ratio = 4
All Other CMOS = 50 MHz (B Outputs On)
Interferer(s)
All LVPECL = 50 MHz
Interferer(s)
CLK1 = 400 MHz
548
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
LVDS (OUT5, OUT6) = 100 MHz
Divide Ratio = 4
All Other CMOS = 50 MHz (B Outputs On)
Interferer(s)
All LVPECL = 50 MHz
Interferer(s)
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution Section only, does not include
PLL or external VCO/VCXO
CLK1 = 400 MHz
275
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)
Divide Ratio = 4
CLK1 = 400 MHz
400
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz
Interferer(s)
All Other LVDS = 50 MHz
Interferer(s)
CLK1 = 400 MHz
374
fs rms
Calculated from SNR of ADC method,
fC = 100 MHz with AIN = 170 MHz
Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz
Interferer(s)
All Other CMOS = 50 MHz (B Output Off)
Interferer(s)
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