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參數(shù)資料
| 型號： | AD9398KSTZ-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/44頁 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE 100MHZ HDMI 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | 視頻 |
| 接口： | HDMI |
| 電源電壓： | 3.15 V ~ 3.47 V |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 配用： | AD9398/PCBZ-ND - BOARD EVALUATION FOR AD9398 |
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AD9398
Rev. 0 | Page 13 of 44
AUDIO BOARD LEVEL MUTING
The audio can be muted through the infoframes or locally
via the serial bus registers. This can be controlled with
Register R0x57, Bits [7:4].
AVI Infoframes
The HDMI TMDS transmission contains infoframes with
specific information for the monitor such as:
Audio information
2 channels to 8 channels of audio identified
Audio coding
Audio sampling frequency
Speaker placement
N and CTS values (for reconstruction of the audio)
Muting
Source information
CD
SACD
DVD
Video information
Video ID code (per CEA861B)
Color space
Aspect ratio
Horizontal and vertical bar information
MPEG frame information (I, B, or P frame)
Vendor (transmitter source) name and product model
This information is the fundamental difference between DVI
and HDMI transmissions and is located in read-only registers
R0x5A to R0xEE. In addition to this information, registers are
provided to indicate that new information has been received.
Registers with addresses ending in 0xX7 or 0xXF beginning at
R0x87 contain the new data flag (NDF) information. These
registers contain the same information and all are reset once
any of them are read. Although there is no external interrupt
signal, it is very easy for the user to read any of these registers to
see if there is new information to be processed.
OUTPUT DATA FORMATS
The AD9398 supports 4:4:4, 4:2:2, double data rate (DDR), and
BT656 output formats. Register 0x25[3:0] controls the output
mode. These modes and the pin mapping are listed in Table 10.
Table 10.
Port
Red
Green
Blue
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
4:4:4
Red/Cr [7:0]
Green/Y [7:0]
Blue/Cb [7:0]
4:2:2
CbCr [7:0]
Y [7:0]
DDR 4:2:2 ↑ CbCr ↓ Y, Y
DDR ↑ 1 G [3:0]
DDR ↑ B [7:4]
DDR ↑ B [3:0]
DDR 4:2:2 ↑ CbCr [11:0]
4:4:4 DDR
DDR ↓ R [7:0]
DDR ↓ G [7:4]
DDR 4:2:2 ↓ Y,Y [11:0]
4:2:2 to 12
CbCr [11:0]
Y [11:0]
1 Arrows in the table indicate clock edge. Rising edge of clock =
↑, falling edge = ↓.
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