參數(shù)資料
型號： AD9398KSTZ-100
廠商： Analog Devices Inc
文件頁數(shù)： 4/44頁
文件大?。?/td> 0K
描述： IC INTERFACE 100MHZ HDMI 100LQFP
標準包裝： 90
應用： 視頻
接口： HDMI
電源電壓： 3.15 V ~ 3.47 V
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
配用： AD9398/PCBZ-ND - BOARD EVALUATION FOR AD9398
AD9398
Rev. 0 | Page 12 of 44
AUDIO PLL SETUP
Data contained in the audio infoframes, among other registers,
define for the AD9398 HDMI receiver not only the type of
audio, but the sampling frequency (fS). The audio infoframe also
contains information about the N and CTS values used to
recreate the clock. With this information, it is possible to
regenerate the audio sampling frequency. The audio clock is
regenerated by dividing the 20-bit CTS value into the TMDS
clock, then multiplying by the 20-bit N value. This yields a
multiple of the sampling frequency of either 128 × fS or 256 × fS.
It is possible for this to be specified up to 1024 × fS.
05678-007
SINK DEVICE
SOURCE DEVICE
1N AND CTS VALUES ARE TRANSMITTED USING THE
AUDIO CLOCK REGENERATION PACKET. VIDEO
CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.
128 × fS
N
VIDEO
CLOCK
128 × fS
TMDS
CLOCK
N1
CTS1
DIVIDE
BY
N
CYCLE
TIME
COUNTER
REGISTER
N
DIVIDE
BY
CTS
MULTIPLY
BY
N
Figure 7. N and CTS for Audio Clock
In order to provide the most flexibility in configuring the audio
sampling clock, an additional PLL is employed. The PLL
characteristics are determined by the loop filter design, the PLL
charge pump current, and the VCO range setting. The loop
filter design is shown in Figure 8.
CP
8nF
CZ
80nF
RZ
1.5k
Ω
FILT
PVD
05678-010
Figure 8. PLL Loop Filter Detail
To fully support all audio modes for all video resolutions up
to 1080p, it is necessary to adjust certain audio-related
registers from their power-on default values. Table 9
describes these registers and gives the recommended
settings.
Table 9. AD9398 Audio Register Settings
Register
Bits
Recommended
Setting
Function
Comments
0x01
7:0
0x00
PLL Divisor (MSBs)
0x02
7:4
0x40
PLL Divisor (LSBs)
7:6
01
VCO Range
5:3
010
Charge Pump Current
The analog video PLL is also used for the audio clock circuit when in
HDMI mode. This is done automatically.
0x03
2
1
PLL Enable
In HDMI mode, this bit enables a lower frequency to be used for
audio MCLK generation.
0x34
4
0
Audio Frequency Mode
Override
Allows the chip to determine the low frequency mode of the audio
PLL.
7
1
PLL Enable
This enables the analog PLL to be used for audio MCLK generation.
6:4
011
MCLK PLL Divisor
When the analog PLL is enabled for MCLK generation, another
frequency divider is provided. These bits set the divisor to 4.
3
0
N/CTS Disable
The N and CTS values should always be enabled.
0x58
2:0
0**
MCLK Sampling Frequency
000 = 128 × fS
001 = 256 × fS
010 = 384 × fS
011 = 512 × fS
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