參數(shù)資料
型號： AD9398KSTZ-100
廠商： Analog Devices Inc
文件頁數(shù)： 24/44頁
文件大?。?/td> 0K
描述： IC INTERFACE 100MHZ HDMI 100LQFP
標準包裝： 90
應用： 視頻
接口： HDMI
電源電壓： 3.15 V ~ 3.47 V
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
配用： AD9398/PCBZ-ND - BOARD EVALUATION FOR AD9398
AD9398
Rev. 0 | Page 30 of 44
0x40—Bits[7:0] CSC B2 LSBs
0x41—Bits[4:0] CSC B3 MSBs
The default value for the 13-bit B3 is 0x1E89.
0x42—Bits[7:0] CSC B3 LSBs
0x43—Bits[4:0] CSC B4 MSBs
The default value for the 13-bit B4 is 0x0291.
0x44—Bits[7:0] CSC B4 LSBs
0x45—Bits[4:0] CSC C1 MSBs
The default value for the 13-bit C1 is 0x0000.
0x46—Bit[7:0] CSC C1 LSBs
0x47—Bit[4:0] CSC C2 MSBs
The default value for the 13 bit C2 is 0x0800.
0x48—Bits[7:0] CSC C2 LSBs
0x49—Bits[4:0] CSC C3 MSBs
The default value for the 13-bit C3 is 0x0E87.
0x4A—Bits[7:0] CSC C3 LSBs
0x4B—Bits[4:0] CSC C4 MSBs
The default value for the 13-bit C4 is 0x18BD.
0x4C—Bits[7:0] CSC C4 LSBs
0x57—Bit[7] AV Mute Override
0x57—Bit[6] AV Mute Value
0x57—Bit[3] Disable AV Mute
0x57—Bit[2] Disable Audio Mute
0x58—Bit[7] MCLK PLL Enable
This bit enables the use of the analog PLL.
0x58—Bits[6:4] MCLK PLL_N
These bits control the division of the MCLK out of the PLL.
Table 18.
PLL_N [2:0]
MCLK Divide Value
0
/1
1
/2
2
/3
3
/4
4
/5
5
/6
6
/7
7
/8
0x58—Bit[3] N_CTS_Disable
This bit makes it possible to prevent the N/CTS packet on the
link from writing to the N and CTS registers.
0x58—Bits[2:0] MCLK fS_N
These bits control the multiple of 128 fS used for MCLK out.
Table 19.
MCLK fS_N [2:0]
fS Multiple
0
128
1
256
2
384
3
512
4
640
5
768
6
896
7
1024
0x59—Bit[6] MDA/MCL PU Disable
This bit disables the inter-MDA/MCL pull-ups.
0x59—Bit[5] CLK Term O/R
This bit allows for overriding during power down.
0 = auto, 1 = manual.
0x59—Bit[4] Manual CLK Term
This bit allows normal clock termination or disconnects this.
0 = normal, 1 = disconnected.
0x59—Bit[2] FIFO Reset UF
This bit resets the audio FIFO if underflow is detected.
0x59—Bit[1] FIFO Reset OF
This bit resets the audio FIFO if overflow is detected.
0x59—Bit[0] MDA/MCL Three-State
This bit three-states the MDA/MCL lines to allow in-circuit
programming of the EEPROM.
0x5A—Bits[6:0] Packet Detect
This register indicates if a data packet in specific sections has
been detected. These seven bits are updated if any specific
packet has been received since last reset or loss of clock detect.
Normal is 0x00.
Table 20.
Packet Detect Bit
Packet Detected
0
AVI infoframe
1
Audio infoframe
2
SPD infoframe
3
MPEG source infoframe
4
ACP packets
5
ISRC1 packets
6
ISRC2 packets
0x5B—Bit[3] HDMI Mode
0 = DVI, 1 = HDMI.
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