參數(shù)資料
型號： AD9398KSTZ-100
廠商： Analog Devices Inc
文件頁數(shù)： 20/44頁
文件大小： 0K
描述： IC INTERFACE 100MHZ HDMI 100LQFP
標準包裝： 90
應用： 視頻
接口： HDMI
電源電壓： 3.15 V ~ 3.47 V
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
配用： AD9398/PCBZ-ND - BOARD EVALUATION FOR AD9398
AD9398
Rev. 0 | Page 27 of 44
0x26—Bit[7] Output Three-State
When enabled, this bit puts all outputs (except SOGOUT) in a
high impedance state. 0 = normal outputs. 1 = all outputs
(except SOGOUT) in high impedance mode. The power-up
default setting is 0.
0x26—Bit[5] S/PDIF Three-State
When enabled, this bit places the S/PDIF audio output pins in a
high impedance state. 0 = normal S/PDIF output. 1 = S/PDIF
pins in high impedance mode. The power-up default setting is
0.
0x26—Bit[4] I2S Three-State
When enabled, this bit places the I2S output pins in a high
impedance state. 0 = normal I2S output. 1 = I2S pins in high
impedance mode. The power-up default setting is 0.
0x26—Bit[3] Power-Down Polarity
This bit defines the polarity of the input power-down pin.
0 = power-down pin is active low. 1 = power-down pin is active
high. The power-up default setting is 1.
0x26—Bits[2:1] Power-Down Pin Function
These bits define the different operational modes of the power-
down pin. These bits are functional only when the power-down
pin is active; when it is not active, the part is powered up and
functioning. 0 = the chip is powered down and all outputs are in
high impedance mode. 1 = the chip remains powered up, but all
outputs are in high impedance mode. The power-up default
setting is 00.
0x26—Bit[0] Power-Down
This bit is used to put the chip in power-down mode. In this
mode, the power dissipation is reduced to a fraction of the
typical power (see Table 1 for exact power dissipation). When in
power-down, the HSOUT, VSOUT, DATACK, and all 30 of the
data outputs are put into a high impedance state. Note that the
SOGOUT output is not put into high impedance. Circuit blocks
that continue to be active during power-down include the
voltage references, sync processing, sync detection, and the
serial register. These blocks facilitate a fast start-up from power-
down. 0 = normal operation. 1 = power-down. The power-up
default setting is 0.
0x27—Bit[7] Auto Power-Down Enable
This bit enables the chip to go into low power mode, or seek
mode if no sync inputs are detected. 0 = auto power-down
disabled. 1 = chip powers down if no sync inputs present. The
power-up default setting is 1.
0x27—Bit[6] HDCP A0 Address
This bit sets the LSB of the address of the HDCP I2C. This
should be set to 1 only for a second receiver in a dual-link
configuration. The power-up default is 0.
0x27—Bit[5] MCLK External Enable
This bit enables the MCLK to be supplied externally. If an
external MCLK is used, then it must be locked to the video
clock according to the CTS and N available in the I2C. Any
mismatch between the internal MCLK and the input MCLK
results in dropped or repeated audio samples. 0 = use internally
generated MCLK. 1 = use external MCLK input. The power-up
default setting is 0.
BT656 GENERATION
0x27—Bit[4] BT656 Enable
This bit enables the output to be BT656 compatible with the
defined start of active video (SAV) and the end of active video
(EAV) controls to be inserted. These require specification of the
number of active lines, active pixels per line, and delays to place
these markers. 0 = disable BT656 video mode. 1 = enable BT656
video mode. The power-up default setting is 0.
0x27—Bit[3] Force DE Generation
This bit allows the use of the internal DE generator in DVI
mode. 0 = internal DE generation disabled. 1 = force DE
generation via programmed registers. The power-up default
setting is 0.
0x27—Bits[2:0] Interlace Offset
These bits define the offset in HSYNCs from Field 0 to Field 1.
The power-up default setting is 000.
0x28—Bits[7:2] VSYNC Delay
These bits set the delay (in lines) from the leading edge of
VSYNC to active video. The power-up default setting is 24.
0x28—Bits[1:0] HSYNC Delay MSBs
Together with Register 0x29, these 10 bits set the delay (in
pixels) from the HSYNC leading edge to the start of active
video. The power-up default setting is 0x104.
0x29—Bits[7:0] HSYNC Delay LSBs
See the HSYNC Delay MSBs section.
0x2A—Bits[3:0] Line Width MSBs
Together with Register 0x2B, these 12 bits set the width of
the active video line (in pixels). The power-up default setting
is 0x500.
0x2B—Bits[7:0] Line Width LSBs
See the Line Width MSBs section.
0x2C—Bits[3:0] Screen Height MSBs
Along with the 8 bits following these 12 bits, set the height of
the active screen (in lines). The power-up default setting is
0x2D0.
0x2D—Bits[7:0] Screen Height LSBs
See the Screen Heights MSBs section.
相關PDF資料
PDF描述
SY100E445JZ IC CONV 4BIT SER/PAR 28-PLCC
556879-6 CONN HOUSING PLUG 6 POS BLACK
AD9985AKSTZ-110 IC INTERFACE 8BIT 110MSPS 80LQFP
AD8170ANZ IC MUX SWITCHING W/AMP 2:1 8DIP
1604062-3 180A HOUSING SUB-ASSY,WHITE
相關代理商/技術參數(shù)
參數(shù)描述
AD9398KSTZ-150 功能描述:IC INTERFACE 150MHZ HDMI 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
AD9410 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 210 MSPS A/D Converter
AD9410/PCB 制造商:Analog Devices 功能描述:EVAL BOARD FOR AD9410 - Bulk
AD9410BSQ 制造商:Analog Devices 功能描述:ADC Single Pipelined 210Msps 10-bit Parallel 80-Pin LQFP EP 制造商:Analog Devices 功能描述:ADC SGL FLASH 210MSPS 10-BIT PARALLEL 80LQFP EP - Trays 制造商:Analog Devices 功能描述:IC 10-BIT ADC
AD9410BSQZ 制造商:Analog Devices 功能描述:ADC Single Pipelined 210Msps 10-bit Parallel 80-Pin LQFP EP 制造商:Analog Devices 功能描述:ADC SGL FLASH 210MSPS 10-BIT PARALLEL 80LQFP EP - Trays
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*