參數(shù)資料
型號： AD9211BCPZ-300
廠商： Analog Devices Inc
文件頁數(shù)： 15/28頁
文件大小： 0K
描述： IC ADC 10BIT 300MSPS 56LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 10
采樣率（每秒）： 300M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 468mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
輸入數(shù)目和類型： 2 個單端，單極；1 個差分，單極
配用： AD9211-200EBZ-ND - BOARD EVAL FOR AD9211-200
AD9211
Rev. 0 | Page 22 of 28
600
–600
–400
–200
0
200
400
–3
–2
–1
0123
EYE
D
IA
G
R
A
M
:
V
O
L
T
A
G
E
(
m
V
)
TIME (ns)
12
10
8
6
4
2
0
–100
0
100
T
IE
JI
T
E
R
HI
S
T
O
G
RAM
(H
it
s)
TIME (ps)
06
04
1-
0
71
Figure 49. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, AD9211-250
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 12.
If it is desired to change the output data format to twos comple-
An output clock signal is provided to assist in capturing data
from the AD9211. The DCO is used to clock the output data
and is equal to the sampling clock (CLK) rate. In single data rate
mode (SDR), data is clocked out of the AD9211 and must be
captured on the rising edge of the DCO. In double data rate
mode (DDR), data is clocked out of the AD9211 and must be
captured on the rising and falling edges of the DCO. See the
timing diagrams shown in Figure 2 and Figure 3 for more
information.
Output Data Rate and Pinout Configuration
The output data of the AD9211 can be configured to drive 10
pairs of LVDS outputs at the same rate as the input clock signal
(single data rate, or SDR, mode), or five pairs of LVDS outputs
at 2× the rate of the input clock signal (double data rate, or DDR,
mode). SDR is the default mode; the device may be reconfigured
for DDR by setting Bit 3 in Register 14 (see Table 13).
Out-of-Range (OR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same
pipeline latency as the digital data. OR is low when the analog
input voltage is within the analog input range and high when
the analog input voltage exceeds the input range, as shown in
Figure 50. OR remains high until the analog input returns to
within the input range and another conversion is completed. By
logically ANDing OR with the MSB and its complement, over-
range high or underrange low conditions can be detected.
1
0
1
OR DATA OUTPUTS
OR
+FS – 1 LSB
+FS – 1/2 LSB
+FS
–FS
–FS + 1/2 LSB
–FS – 1/2 LSB
1111
0000
1111
0000
1111
1110
0001
0000
06
04
1-
06
2
Figure 50. OR Relation to Input Voltage and Output Data
TIMING
The AD9211 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9211.
These transients can degrade the converter’s dynamic performance.
The AD9211 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are valid
on the rising edge of DCO.
The lowest typical conversion rate of the AD9211 is 40 MSPS. At
clock rates below 1 MSPS, the AD9211 assumes the standby mode.
RBIAS
The AD9211 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resister should have a 1%
tolerance and is used to set the master current reference of the
ADC core.
AD9211 CONFIGURATION USING THE SPI
The AD9211 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or readback) serially in
one-byte words. Each byte may be further divided down into
fields, which are documented in the Memory Map section.
There are three pins that define the serial port interface or SPI
to this particular ADC. They are the SPI SCLK/DFS, SPI
SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used
to synchronize the read and write data presented the ADC. The
SDIO/DCS (serial data input/output) is a dual-purpose pin that
allows data to be sent and read from the internal ADC memory
map registers. The CSB is an active low control that enables or
disables the read and write cycles (see Table 9).
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