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參數(shù)資料
| 型號(hào)： | AD9211BCPZ-300 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 300MSPS 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 300M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 468mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
| 配用： | AD9211-200EBZ-ND - BOARD EVAL FOR AD9211-200 |
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AD9211
Rev. 0 | Page 20 of 28
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9211 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ pin and CLK
pin via a transformer or capacitors. These pins are biased
internally and require no additional bias.
Figure 42 shows one preferred method for clocking the AD9211.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9211 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9211 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
0.1F
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
AD9211
MINI-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
SCHOTTKY
DIODES:
HSM2812
06
04
1-
0
59
Figure 42. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
performance.
100
0.1F
240
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
50*
CLK
*50 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9211
PECL DRIVER
CLOCK
INPUT
CLOCK
INPUT
06041-
060
Figure 43. Differential PECL Sample Clock
CLOCK
INPUT
CLOCK
INPUT
100
0.1F
50*
LVDS DRIVER
50*
CLK
*50 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9211
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
06041-
067
Figure 44. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 45). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
0.1F
39k
CMOS DRIVER
50*
OPTIONAL
100
0.1F
CLK
*50 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9211
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLOCK
INPUT
06
04
1-
0
68
Figure 45. Single-Ended 1.8 V CMOS Sample Clock
0.1F
CMOS DRIVER
CLK
*50 RESISTOR IS OPTIONAL.
0.1F
CLK–
CLK+
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
ADC
AD9211
CLOCK
INPUT
50*
OPTIONAL
100
06
041
-06
9
Figure 46. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9211 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9211. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the AD9211 Configuration
Using the SPI section for more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
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