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參數(shù)資料
| 型號(hào)： | AD8332-EVALZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 25/56頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD8332 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | X-AMP® |
| 每 IC 通道數(shù)： | 1 - 單 |
| 放大器類(lèi)型： | 可變?cè)鲆?br> |
| 輸出類(lèi)型： | 差分 |
| 轉(zhuǎn)換速率： | 1100 V/µs |
| -3db帶寬： | 100MHz |
| 電流 - 輸出 / 通道： | 45mA |
| 工作溫度： | -40°C ~ 85°C |
| 電流供應(yīng)（主 IC）： | 27.5mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 板類(lèi)型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD8332 |
| 產(chǎn)品目錄頁(yè)面： | 775 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD8332ACPZ-R2-ND - IC AMP VGA PREAMP PROGR 32-LFCSP AD8332ACPZ-R7DKR-ND - IC AMP VAR GAIN 2CHAN 32-LFCSP AD8332ACPZ-R7CT-ND - IC AMP VAR GAIN 2CHAN 32-LFCSP AD8332ARUZ-R7-ND - IC AMP VAR GAIN 2CHAN 28TSSOP AD8332ACPZ-R7TR-ND - IC AMP VAR GAIN 2CHAN 32LFCSP AD8332ARUZ-RL-ND - IC AMP VAR GAIN 2CHAN 28TSSOP AD8332ACPZ-RL-ND - IC AMP VAR GAIN 2CHAN 32LFCSP AD8332ARUZ-ND - IC VGA DUAL W/PREAMP LN 28-TSSOP AD8332ACP-R2DKR-ND - IC VGA DUAL W/PREAMP LN 32-LFCSP AD8332ACP-R2CT-ND - IC VGA DUAL W/PREAMP LN 32-LFCSP 更多... |
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AD8331/AD8332/AD8334
Rev. G | Page 31 of 56
Gain Input
The GAIN pin is common to both channels of the AD8332. The
input impedance is nominally 10 MΩ, and a bypass capacitor
from 100 pF to 1 nF is recommended.
Parallel connected devices can be driven by a common voltage
source or DAC. Decoupling should take into account any band-
width considerations of the drive waveform, using the total
distributed capacitance.
If gain control noise in LO gain mode becomes a factor, main-
taining ≤15 nV/√Hz noise at the GAIN pin ensures satisfactory
noise performance. Internal noise prevails below 15 nV/√Hz at
the GAIN pin. Gain control noise is negligible in HI gain mode.
VCM Input
The common-mode voltage of Pin VCM, Pin VOL, and Pin VOH
defaults to 2.5 V dc. With output ac-coupled applications, the
VCM pin is unterminated; however, it must still be bypassed in
close proximity for ac grounding of internal circuitry. The VGA
outputs can be dc connected to a differential load, such as an
ADC. Common-mode output voltage levels between 1.5 V and
3.5 V can be realized at Pin VOH and Pin VOL by applying the
desired voltage at Pin VCM. DC-coupled operation is not
recommended when driving loads on a separate PC board.
The voltage on the VCM pin is sourced by an internal buffer
with an output impedance of 30 Ω and a ±2 mA default output
current (see Figure 83). If the VCM pin is driven from an external
source, its output impedance should be <<30 Ω, and its current
drive capability should be >>2 mA. If the VCM pins of several
devices are connected in parallel, the external buffer should be
capable of overcoming their collective output currents. When a
common-mode voltage other than 2.5 V is used, a voltage-
limiting resistor, RCLMP, is needed to protect against overload.
03
19
9-
0
83
VCM
NEW VCM
RO << 30
100pF
2mA MAX
30
0.1F
INTERNAL
CIRCUITRY
AC GROUNDING FOR
INTERNAL CIRCUITRY
Figure 83. VCM Interface
Logic Inputs—ENB, MODE, and HILO
The input impedance of all enable pins is nominally 25 kΩ and
can be pulled up to 5 V (a pull-up resistor is recommended) or
driven by any 3 V or 5 V logic families. The enable pin, ENB,
powers down the VGA; when pulled low, the VGA output voltages
are near ground. Multiple devices can be driven from a common
mation about circuit functions controlled by the enable pins.
Pin HILO is compatible with 3 V or 5 V CMOS logic families. It
is either connected to ground or pulled up to 5 V, depending on
the desired gain range and output noise.
Optional Output Voltage Limiting
The RCLMP pin provides the user with a means to limit the
output voltage swing when used with loads that have no
provisions for prevention of input overdrive. The peak-to-peak
limited voltage is adjusted by a resistor to ground (see Table 8
for a list of several voltage levels and corresponding resistor
values). Unconnected, the default limiting level is 4.5 V p-p.
Note that third harmonic distortion increases as waveform
amplitudes approach clipping. For lowest distortion, the clamp level
should be set higher than the converter input span. A clamp level
of 1.5 V p-p is recommended for a 1 V p-p linear output range,
2.7 V p-p for a 2 V p-p range, or 1 V p-p for a 0.5 V p-p operation.
The best solution is determined experimentally. Figure 84 shows
third harmonic distortion as a function of the limiting level for
a 2 V p-p output signal. A wider limiting level is desirable in HI
gain mode.
–20
–30
–40
–50
–60
–70
–80
1.52.0
2.53.0
4.0
3.5
4.5
5.0
HD
3(
d
B
c)
CLAMP LIMIT LEVEL (V p-p)
03
19
9-
08
4
VGAIN = 0.75V
HILO = LO
HILO = HI
Figure 84. HD3 vs. Clamping Level for 2 V p-p Differential Input
Table 8. Clamp Resistor Values
Clamp Level (V p-p)
Clamp Resistor Value (kΩ)
HILO = LO
HILO = HI
0.5
1.21
1.0
2.74
2.21
1.5
4.75
4.02
2.0
7.5
6.49
2.5
11
9.53
3.0
16.9
14.7
3.5
26.7
23.2
4.0
49.9
39.2
4.4
100
73.2
Output Decoupling
When driving capacitive loads greater than about 10 pF, or long
circuit connections on other boards, an output network of resistors
and/or ferrite beads can be useful to ensure stability. These
components can be incorporated into a Nyquist filter such as
84.5 Ω. For example, all the evaluation boards for this series
incorporate 100 Ω in parallel with a 120 nH bead. Lower value
resistors are permissible for applications with nearby loads or
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