參數(shù)資料
型號(hào)： AD8332-EVALZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/56頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD8332
標(biāo)準(zhǔn)包裝： 1
系列： X-AMP®
每 IC 通道數(shù)： 1 - 單
放大器類型： 可變?cè)鲆?br>
輸出類型： 差分
轉(zhuǎn)換速率： 1100 V/µs
-3db帶寬： 100MHz
電流 - 輸出 / 通道： 45mA
工作溫度： -40°C ~ 85°C
電流供應(yīng)（主 IC）： 27.5mA
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 5.5 V
板類型： 完全填充
已供物品： 板
已用 IC / 零件： AD8332
產(chǎn)品目錄頁(yè)面： 775 (CN2011-ZH PDF)
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AD8331/AD8332/AD8334
Rev. G | Page 28 of 56
VGA Noise
In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. While
the input-referred noise of the LNA limits the minimum resolvable
input signal, the output-referred noise, which depends primarily
on the VGA, limits the maximum instantaneous dynamic range
that can be processed at any one particular gain control voltage.
This limit is set in accordance with the quantization noise floor
of the ADC.
Output- and input-referred noise as a function of VGAIN are plotted
in Figure 25 and Figure 27 for the short circuited input conditions.
The input noise voltage is simply equal to the output noise divided
by the measured gain at each point in the control range.
The output-referred noise is flat over most of the gain range
because it is dominated by the fixed output-referred noise of the
VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz
in HI gain mode. At the high end of the gain control range, the
noise of the LNA and the noise of the source prevail. The input-
referred noise reaches its minimum value near the maximum
gain control voltage, where the input-referred contribution of
the VGA becomes very small.
At lower gains, the input-referred noise, and thus noise figure,
increases as the gain decreases. The instantaneous dynamic
range of the system is not lost, however, because the input
capacity increases with it. The contribution of the ADC noise
floor has the same dependence as well. The important relationship
is the magnitude of the VGA output noise floor relative to that
of the ADC.
With its low output-referred noise levels, these devices ideally
drive low voltage ADCs. The converter noise floor drops 12 dB
for every two bits of resolution and drops at lower input full-
scale voltages and higher sampling rates. ADC quantization
noise is discussed in the Applications Information section.
The preceding noise performance discussion applies to a
differential VGA output signal. Although the LNA noise
performance is the same in single-ended and differential
applications, the VGA performance is not. The noise of the
VGA is significantly higher in single-ended usage because the
contribution of its bias noise is designed to cancel in the differential
signal. A transformer can be used with single-ended applications
when low noise is desired.
Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resultant noise is proportional to the output
signal level and usually only evident when a large signal is present.
Its effect is observable only in LO gain mode where the noise
floor is substantially lower. The gain interface includes an
on-chip noise filter, which reduces this effect significantly at
frequencies above 5 MHz. Care should be taken to minimize
noise impinging at the GAIN input. An external RC filter can be
used to remove VGAIN source noise. The filter bandwidth should be
sufficient to accommodate the desired control bandwidth.
Common-Mode Biasing
An internal bias network connected to a midsupply voltage
establishes common-mode voltages in the VGA and postamp.
An externally bypassed buffer maintains the voltage. The bypass
capacitors form an important ac ground connection because
the VCM network makes a number of important connections
internally, including the center tap of the VGA differential input
attenuator, the feedback network of the VGA fixed gain amplifier,
and the feedback network of the postamp in both gain settings.
For best results, use a 1 nF capacitor and a 0.1 μF capacitor in
parallel, with the 1 nF capacitor nearest to the VCM pin. Separate
VCM pins are provided for each channel. For dc coupling to a 3 V
ADC, the output common-mode voltage is adjusted to 1.5 V by
biasing the VCM pin.
POSTAMPLIFIER
The final stage has a selectable gain of 3.5 dB (×1.5) or 15.5 dB
(×6), set by the HILO logic pin. Figure 79 is a simplified block
diagram.
0
31
99
-0
79
Gm2
+
–
Gm1
VOH
VOL
VCM
Gm1
Gm2
F1
F2
Figure 79. Postamplifier Block Diagram
Separate feedback attenuators implement the two gain settings.
These are selected in conjunction with an appropriately scaled
input stage to maintain a constant 3 dB bandwidth between the
two gain modes (~150 MHz). The slew rate is 1200 V/μs in HI gain
mode and 300 V/μs in LO gain mode. The feedback networks
for HI and LO gain modes are factory trimmed to adjust the
absolute gains of each channel.
Noise
The topology of the postamp provides constant input-referred
noise with the two gain settings and variable output-referred
noise. The output-referred noise in HI gain mode increases
(with gain) by four. This setting is recommended when driving
converters with higher noise floors. The extra gain boosts the
output signal levels and noise floor appropriately. When driving
circuits with lower input noise floors, the LO gain mode optimizes
the output dynamic range.
Although the quantization noise floor of an ADC depends on a
number of factors, the 48 nV/√Hz and 178 nV/√Hz levels are
well suited to the average requirements of most 12-bit and 10-bit
converters, respectively. An additional technique, described in
the Applications Information section, can extend the noise floor
even lower for possible use with 14-bit ADCs.
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