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| 型號： | AD8332-EVALZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD8332 |
| 標準包裝： | 1 |
| 系列： | X-AMP® |
| 每 IC 通道數(shù)： | 1 - 單 |
| 放大器類型： | 可變增益 |
| 輸出類型： | 差分 |
| 轉換速率： | 1100 V/µs |
| -3db帶寬： | 100MHz |
| 電流 - 輸出 / 通道： | 45mA |
| 工作溫度： | -40°C ~ 85°C |
| 電流供應（主 IC）： | 27.5mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 板類型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD8332 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
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AD8331/AD8332/AD8334
Rev. G | Page 30 of 56
APPLICATIONS INFORMATION
LNA—EXTERNAL COMPONENTS
The LMD pin (connected to the bias circuitry) must be bypassed to
ground and signal sourced to the INH pin, which is capacitively
coupled using 2.2 nF to 0.1 μF capacitors (see Figure 81).
The unterminated input impedance of the LNA is 6 kΩ. The
user can synthesize any LNA input resistance between 50 Ω and
6 kΩ. RIZ is calculated according to Equation 6 or selected from
()
IN
IZ
R
–
kΩ
6
kΩ
33
×
=
(6)
Table 7. LNA External Component Values for Common
Source Impedances
RIN (Ω)
RIZ (Nearest STD 1% Value, Ω)
CSH (pF)
50
280
22
75
412
12
100
562
8
200
1.13 k
1.2
500
3.01 k
None
6 k
∞
None
When active input termination is used, a decoupling capacitor (CIS)
is required to isolate the input and output bias voltages of the LNA.
The shunt input capacitor, CSH, reduces gain peaking at higher
frequencies where the active termination match is lost due to
the gain roll-off of the LNA at high frequencies. The value of CSH
diminishes as RIN increases to 500 Ω, at which point no capacitor is
required. Suggested values for CSH for 50 Ω ≤ RIN ≤ 200 Ω are
shown in Table 7.
When a long trace to Pin INH is unavoidable, or if both LNA
outputs drive external circuits, a small ferrite bead (FB) in series
with Pin INH preserves circuit stability with negligible effect on
noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or
equivalent). Other values can prove useful.
Figure 82 shows the interconnection details of the LNA output.
Capacitive coupling between the LNA outputs and the VGA
inputs is required because of the differences in their dc levels
and the need to eliminate the offset of the LNA. Capacitor values
of 0.1 μF are recommended. There is a 0.4 dB loss in gain
between the LNA output and the VGA input due to the 5 Ω
output resistance. Additional loading at the LOP and LON
outputs affects LNA gain.
21
22
23
24
28
25
26
27
15
16
20
17
18
19
8
7
6
5
1
4
3
2
14
13
9
12
11
10
VCM2
RCLMP
COMM
VOL2
VOH2
VIP2
GAIN
VIN2
LOP2
COM2
LMD2
LON2
VPS2
INH2
COM1
LOP1
LMD1
LON1
VPS1
INH1
VOH1
ENB
VIP1
VCM1
VIN1
VPSV
VOL1
HILO
0.1F
CIZ*
CSH*
RIZ*
CLMD
0.1F
1nF
5V
1nF
5V
+5V
*
VGA OUT
5V
1nF
0.1F
LNA OUT
1nF
VGAIN
FB
1nF
0.1F
1nF
0.1F
*SEE TEXT
03
19
9-
081
LNA
SOURCE
Figure 81. Basic Connections for a Typical Channel (AD8332 Shown)
03199-
082
VIN
VIP
LOP
VCM
100
50
100
LON
RIZ
CSH
TO EXT
CIRCUIT
TO EXT
CIRCUIT
LNA
DECOUPLING
RESISTOR
LNA
DECOUPLING
RESISTOR
50
5
LNA
3.25V
2.5V
Figure 82. Interconnections of the LNA and VGA
Both LNA outputs are available for driving external circuits.
Pin LOP should be used in those instances when a single-ended
LNA output is required. The user should be aware of stray
capacitance loading of the LNA outputs, in particular LON. The
LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is
routed to a remote PC board, it tolerates a load capacitance up
to 100 pF with the addition of a 49.9 Ω series resistor or ferrite
75 Ω/100 MHz bead.
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