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參數(shù)資料
| 型號： | AD8191AASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HDMI/DVI SWITCH 4:1 100LQFP |
| 標準包裝： | 1 |
| 功能： | 開關(guān)，DVI/HDMI |
| 電路： | 1 x 16:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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AD8191A
Rev. 0 | Page 13 of 28
THEORY OF OPERATION
INTRODUCTION
The primary function of the AD8191A is to switch one of four
(HDMI or DVI) single-link sources to one output. Each HDMI/
DVI link consists of four differential, high speed channels and
four auxiliary single-ended, low speed control signals. The high
speed channels include a data-word clock and three transition
minimized differential signaling (TMDS) data channels running at
10× the data-word clock frequency for data rates up to 1.65 Gbps.
The four low speed control signals are 5 V tolerant bidirectional
lines that can carry configuration signals, HDCP encryption, and
other information, depending upon the specific application.
All four high speed TMDS channels in a given link are identical;
that is, the pixel clock can be run on any of the four TMDS
channels. Transmit and receive channel compensation is provided
for the high speed channels where the user can (manually)
select among a number of fixed settings.
The AD8191A has two control interfaces. Users have the option
of controlling the part through either the parallel control interface
or the I2C serial control interface. The AD8191A has eight user-
programmable I2C slave addresses to allow multiple AD8191As
to be controlled by a single I2C bus. A RESET pin is provided to
restore the control registers of the AD8191A to default values.
In all cases, serial programming values override any prior parallel
programming values, and any use of the serial control interface
disables the parallel control interface until the AD8191A is reset.
INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
VTTI power supply through a pair of single-ended 50 Ω on-chip
resistors, as shown in Figure 25. The input terminations can be
optionally disconnected for approximately 100 ms following a
source switch. The user can program which of the 16 high speed
input channels employs this feature by selectively programming
the associated RX_PT bits in the input termination pulse registers
through the serial control interface. Additionally, all the input
terminations can be disconnected by programming the RX_TO
bit in the receiver settings register. By default, the input termination
is enabled. The input terminations are enabled and cannot be
switched when programming the AD8191A through the parallel
control interface.
CABLE
EQ
50
IP_xx
IN_xx
AVEE
VTTI
0
70
13
-0
25
Figure 25. High Speed Input Simplified Schematic
The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 12 dB. The user
can individually control the equalization level of the eight high
speed input channels by selectively programming the associated
RX_EQ bits in the receive equalizer register through the serial
control interface. Alternately, the user can globally control the
equalization level of all eight high speed input channels by setting
the PP_EQ pin of the parallel control interface. No specific
cable length is suggested for a particular equalization setting
because cable performance varies widely between manufacturers;
however, in general, the equalization of the AD8191A can be set
to 12 dB without degrading the signal integrity, even for short
input cables. At the 12 dB setting, the AD8191A can equalize
more than 20 meters of 24 AWG cable at 1.65 Gbps.
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through a 50 Ω on-chip resistor (see
Figure 26). This termination is user-selectable; it can be turned
on or off by programming the TX_PTO bit of the transmitter
settings register through the serial control interface, or by
setting the PP_OTO pin of the parallel control interface.
VTTO
50
OPx
ONx
AVEE
DISABLE
IOUT
0
70
13
-0
26
Figure 26. High Speed Output Simplified Schematic
The output termination resistors of the AD8191A back-terminate
the output TMDS transmission lines. These back-terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8191A
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
The AD8191A output has a disable feature that places the
outputs in a tristate mode. This mode is enabled by programming
the HS_EN bit of the high speed device modes register through
the serial control interface or by setting the PP_EN pin of the
parallel control interface. Larger wire-OR’ed arrays can be
constructed using the AD8191A in this mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8191ASTZ | IC INTERFACE HDMI/DVI 100-LQFP |
| AD8192ACPZ-RL7 | IC SW MUX HDMI/DVI 2:1 56LFCSP |
| AD8193ACPZ | IC SWITCH TMDS BUFF 2:1 32LFCSP |
| AD8194ACPZ-R7 | IC SWITCH TMDS BUFF 2:1 32LFCSP |
| AD8195ACPZ | IC BUFF HDMI/DVI W/EQUAL 40LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8191AASTZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4:1 HDMI/DVI Switch with Equalization |
| AD8191AASTZ-RL | 功能描述:IC SWITCH HDMI/DVI 4:1 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標準包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8191AASTZ-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4:1 HDMI/DVI Switch with Equalization |
| AD8191ACPZ | 制造商:Analog Devices 功能描述:- Bulk |
| AD8191A-EVALZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD8191A - Bulk |
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