參數(shù)資料
型號: AD8191AASTZ
廠商: Analog Devices Inc
文件頁數(shù): 13/28頁
文件大?。?/td> 0K
描述: IC HDMI/DVI SWITCH 4:1 100LQFP
標準包裝: 1
功能: 開關,DVI/HDMI
電路: 1 x 16:1
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
AD8191A
Rev. 0 | Page 20 of 28
PARALLEL INTERFACE CONFIGURATION REGISTERS
The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and
PP_OCL pins. This interface is only accessible after the part is reset and before any registers are accessed using the serial control interface.
The state of each pin is set by tying it to 3.3 V (Logic 1) or 0 V (Logic 0).
Table 18. Parallel Interface Register Map
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
High speed
channel
enable
High speed source select
High Speed
Device Modes
PP_EN
0
PP_CH[1]
PP_CH[0]
Auxiliary
switch enable
Auxiliary switch source select
Auxiliary
Device Modes
1
0
PP_CH[1]
PP_CH[0]
Input termination
on/off select
(termination always on)
Receiver
Settings
1
Source A and Source B input termination select (termination always off )
Input
Termination
Pulse Register 1
0
Source C and Source D input termination select (termination always off )
Input
Termination
Pulse Register 2
0
Source A and Source B input equalization level select
Receive
Equalizer
Register 1
PP_EQ
Source C and Source D input equalization level select
Receive
Equalizer
Register 2
PP_EQ
Output pre-emphasis
level select
Output
termination
on/off select
Output current level
select
Transmitter
Settings
PP_PE[1]
PP_PE[0]
PP_OTO
PP_OCL
HIGH SPEED DEVICE MODES REGISTER
PP_EN: High Speed (TMDS) Channels Enable Bit
Table 19. PP_EN Description
PP_EN
Description
0
High speed channels off, low power/standby mode
1
High speed channels on
PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus
Table 20. High Speed Switch Mapping
PP_CH[1:0]
O[3:0]
Description
00
A[3:0]
High Speed Source A switched to output
01
B[3:0]
High Speed Source B switched to output
10
C[3:0]
High Speed Source C switched to output
11
D[3:0]
High Speed Source D switched to output
AUXILIARY DEVICE MODES REGISTER
PP_CH[1:0]: Auxiliary Switch Source Select Bus
Table 21. Auxiliary Switch Mapping
PP_CH[1:0]
AUX_COM[3:0]
Description
00
AUX_A[3:0]
Auxiliary Source A switched to
output
01
AUX_B[3:0]0
Auxiliary Source B switched to
output
10
AUX_C[3:0]
Auxiliary Source C switched to
output
11
AUX_D[3:0]
Auxiliary Source D switched to
output
RECEIVER SETTINGS REGISTER
High speed (TMDS) channels input termination is fixed to on
when using the parallel interface.
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