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AD8158
Rev. B | Page 5 of 36
I2C TIMING SPECIFICATIONS
SCL
S
Sr
NOTES
1. S = START CONDITION.
2. Sr = REPEAT START.
3. P = STOP.
S
P
SDA
tF
tLOW
tHD;STA
tHD;DAT
tSU;DAT
tSU;STA
tHD;STA
tHIGH
tR
tF
tSU;STO
tR
tBUF
066
46
-10
2
Figure 2. I2C Timing Diagram
Table 2. I2C Timing Parameters
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fSCL
0
400+
kHz
Hold Time for a Start Condition
tHD;STA
0.6
渭s
Setup Time for a Repeated Start Condition
tSU;STA
0.6
渭s
Low Period of the SCL Clock
tLOW
1.3
渭s
High Period of the SCL Clock
tHIGH
0.6
渭s
Data Hold Time
tHD;DAT
0
渭s
Data Setup Time
tSU;DAT
10
ns
Rise Time for Both SDA and SCL
tR
1
300
ns
Fall Time for Both SDA and SCL
tF
1
300
ns
Setup Time for Stop Condition
tSU;STO
0.6
渭s
Bus Free Time Between a Stop and a Start Condition
tBUF
1
渭s
Bus Free Time After a Reset
1
渭s
Reset Pulse Width1
10
ns
1 Reset pulse width is defined as the time RESETB is held below the logic low threshold (VIL) listed in Table 1 while the DVCC supply is within the operating range in Table 1.
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