參數(shù)資料
型號(hào): AD8158ACPZ
廠商: Analog Devices Inc
文件頁數(shù): 25/36頁
文件大?。?/td> 0K
描述: IC MUX/DEMUX QUAD 2X1 100LFCSP
產(chǎn)品變化通告: AD8158 Change of Default Settings 13/Aug/2009
標(biāo)準(zhǔn)包裝: 1
系列: XStream™
功能: 多路復(fù)用器/多路分解器
電路: 4 x 2:1
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 1.6 V ~ 3.6 V
電流 - 電源: 780mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 100ピンLFCSP-VQ(12x12)
包裝: 托盤
AD8158
Rev. B | Page 31 of 36
SUPPLY SEQUENCING
Ideally, all power supplies should be brought up to the appropri-
ate levels simultaneously (power supply requirements are set by
the supply limits in Table 1 and the absolute maximum ratings
listed in Table 3). In the event that the power supplies to the
AD8158 are brought up separately, the supply power-up sequence
is as follows: DVCC is powered first, followed by VCC, and lastly
VTTI and VTTO. The power-down sequence is reversed, with VTTI
and VTTO being powered off first.
VTTI and VTTO contain ESD protection diodes to the VCC power
domain (see Figure 38 and Figure 39). To avoid a sustained high
current condition in these devices (ISUSTAINED < 64 mA), the VTTI
and VTTO supplies should be powered on after VCC and should
be powered off before VCC.
If the system power supplies have a high impedance in the
powered off state, then supply sequencing is not required
provided the following limits are observed:
Peak current from VTTI or VTTO to VCC < 200 mA
Sustained current from VTTI or VTTO to VCC < 64 mA
RESET
On initial power up or at any point during operation the
AD8158 register set can be restored to the default values by
pulling the RESETB pin low. Reset pulse width is defined as the
time RESETB is held below the logic low threshold (VIL) listed
in Table 1 while the DVCC supply is within the operating range
in Table 1. During normal operation the RESETB pin must be
pulled up to DVCC. A software reset is available by writing value
0x01 to the Reset register at address 0x00. This register
is write only.
SINGLE SUPPLY vs. MULTIPLE SUPPLY
OPERATION
The AD8158 supports a flexible supply voltage of 1.8 V to 3.3 V.
For some dc-coupled links, 1.2 V or ground-referenced signaling
may be desired. In these cases, the AD8158 can be run with a
split supply configuration. An example is shown in Figure 47.
TX
RX
0V
VTTO
VCC
DVCC
50
50
50
50
VTTI
CML
AD8158
Z0
VEE = –3.3V (OR –1.8V)
VOH = 0mV
VOL = –400mV
Z0
+
MCU
MCU_VDD
MCU_VSS
DVCC
TO AD8158
I2C_SCL
I2C_SDA
VEE
ADuM1250
06
64
6-
14
8
Figure 47. Multiple Supply Operation
Table 21. Alternate Supply Configuration Examples
Signal Level
VCC, VTTI, VTTO
VEE
1.2 V CML
1.2 V
2.1 V ≤VEE ≤ 0.6 V
GND 400 mV diff
GND
3.3 V ≤VEE ≤ 1.8 V
The AD8158 control signals are always referenced between
DVCC and VEE and, when using a split supply configuration,
logic level-shift circuits should be used. The evaluation board
design shows the use of the Analog Devices, Inc., ADUM1250
I2C isolator and a level shifter to level-shift the SCL and SDA
signals (for information about the evaluation board, see the
Evaluation of DC-Coupled Links
When evaluating the AD8158 dc-coupled, note that most lab
equipment is ground referenced whereas the AD8158 high
speed I/O are connected by 50 Ω on-die termination resistors to
VTTI and VTTO. To interface the AD8158 to ground-referenced,
high speed instrumentation (for example, the 50 Ω inputs of a
high speed oscilloscope), it is necessary to level-shift the outputs by
either using a dc-blocking network or powering the AD8158
between ground and a negative supply.
For example, to evaluate 1.8 V dc-coupled transmitter perfor-
mance with a 50 Ω ground-referenced oscilloscope, use the
following supply configuration:
VCC = VTTO = VTTI = Ground
VEE = 1.8 V
Ground < DVCC < 1.5 V
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