參數(shù)資料
型號(hào)： AD7938BCPZ-6
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 8CH 625KSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 625k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 7.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 托盤(pán)
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極；4 個(gè)偽差分，單極；7 偽差分，單極
配用： EVAL-AD7938CBZ-ND - EVAL BOARD FOR AD7938
AD7938-6
Data Sheet
Rev. C | Page 28 of
AD7938-6 to ADSP-21065L Interface
32
Figure 43 shows a typical interface between the AD7938-6 and
the ADSP-21065L SHARC processor. This interface is an
example of one of three DMA handshake modes. The MSx
control line is actually three memory select lines. Internal
ADDR25 to 24 are decoded into MS3 to 0, these lines are then
asserted as chip selects. The DMAR1 (DMA request 1) is used in
this setup as the interrupt to signal the end of conversion. The
rest of the interface is a standard handshaking operation.
AD7938-6*
ADSP-21065L*
WR
DB0 TO DB11
D0 TO D31
A0 TO A23
MSX
DMAR1
BUSY
CS
CONVST
DSP/USER SYSTEM
WR
RD
*ADDITIONAL PINS REMOVED FOR CLARITY.
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
04
75
1-
04
6
Figure 43. Interfacing to the ADSP-21065L
AD7938-6 to TMS32020, TMS320C25, and TMS320C5x
Interface
Parallel interfaces between the AD7938-6 and the TMS32020,
TMS320C25, and TMS320C5x family of DSPs are shown in
Figure 44. The memory mapped address chosen for the AD7938-6
should be chosen to fall in the I/O memory space of the DSPs.
The parallel interface on the AD7938-6 is fast enough to
interface to the TMS32020 with no extra wait states. If high
speed glue logic, such as 74AS devices, is used to drive the RD
and the WR lines when interfacing to the TMS320C25, then
again, no wait states are necessary. However, if slower logic is
used, data accesses may be slowed sufficiently when reading
from, and writing to, the part to require the insertion of one
wait state. Extra wait states are necessary when using the
TMS320C5x at their fastest clock speeds (see the TMS320C5x
User’s Guide for details).
Data is read from the ADC using the following instruction
IN D, ADC
where:
D is the data memory address.
ADC is the AD7938-6 address.
AD7938-6*
TMS32020/
TMS320C25/
TMS320C50*
WR
RD
DB11 TO DB0
DMD0 TO DMD15
A0 TO A15
IS
READY
INTX
BUSY
CS
EN
CONVST
DSP/USER SYSTEM
TMS320C25
ONLY
R/W
STRB
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
ADDRESS
DECODER
MSC
DATA BUS
04
75
1-
04
7
Figure 44. Interfacing to the TMS32020/TMS320C25/TMS320C5x
AD7938-6 to 80C186 Interface
Figure 45 shows the AD7938-6 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer
can occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7938-6 has finished a conversion, the
BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next
conversion.
AD7938-6*
80C186*
WR
DB0 TO DB11
AD0 TO AD15
A16 TO A19
ALE
DRQ1
BUSY
CS
QR
S
CONVST
MICROPROCESSOR/
USER SYSTEM
WR
RD
L PINS OMITTED FOR CLARITY
ADDRESS/DATA BUS
ADDRESS BUS
*ADDITIONA
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
04
75
1
-04
8
Figure 45. Interfacing to the 80C186
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