參數(shù)資料
型號(hào)： AD7938BCPZ-6
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/32頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 8CH 625KSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 625k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 7.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 托盤
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極；4 個(gè)偽差分，單極；7 偽差分，單極
配用： EVAL-AD7938CBZ-ND - EVAL BOARD FOR AD7938
Data Sheet
AD7938-6
Rev. C | Page 27 of 32
THROUGHPUT (kSPS)
P
O
WE
R
(
m
W)
7
1
2
3
4
5
6
0
100
200
300
400
500
700
600
04
75
1-
03
0
POWER vs. THROUGHPUT RATE
TA = 25°C
A considerable advantage of powering the ADC down after a
conversion is that the power consumption of the part is
significantly reduced at lower throughput rates. When using the
different power modes, the AD7938-6 is only powered up for
the duration of the conversion. Therefore, the average power
consumption per cycle is significantly reduced. Figure 40 shows
a plot of the power vs. the throughput rate when operating in
autostandby mode for both VDD = 5 V and 3 V.
VDD = 5V
VDD = 3V
AD7938-6*
For example, if the device runs at a throughput rate of 10 kSPS,
then the overall cycle time would be 100 μs. If the maximum
CLKIN frequency of 10 MHz is used, the conversion time accounts
for only 1.315 μs of the overall cycle time while the AD7938-6
remains in standby mode for the remainder of the cycle.
If an external reference is used, the power-up time reduces to
600 ns; therefore, the AD7938-6 remains in standby for a
greater length of time in every cycle. Additionally, the current
consumption, when converting, would be lower than the
specified maximum of 1.5 mA with VDD = 5 V, or 1.2 mA with
VDD = 3 V.
Figure 41 shows a plot of the power vs. the throughput rate
when operating in normal mode for both VDD = 5 V and
VDD = 3 V. Again, when using an external reference, the current
consumption when converting will be lower than the specified
maximum. In both plots, the figures apply when using the
internal reference.
THROUGHPUT (kSPS)
0
0.2
0
20
40
60
80
120
100
04
75
1-
02
9
P
O
WE
R
(
m
W)
2.0
0.8
1.0
1.2
1.4
1.6
1.8
0.6
0.4
TA = 25°C
VDD = 5V
VDD = 3V
Figure 40. Power vs. Throughput in Autostandby
Mode Using Internal Reference
Figure 41. Power vs. Throughput in Normal Mode Using Internal Reference
MICROPROCESSOR INTERFACING
AD7938-6 to ADSP-21xx Interface
Figure 42 shows the AD7938-6 interfaced to the ADSP-21xx
series of DSPs as a memory mapped device. A single wait state
may be necessary to interface the AD7938-6 to the ADSP-21xx
depending on the clock speed of the DSP. The wait state can be
programmed via the data memory wait state control register of
the ADSP-21xx (see the ADSP-21xx family User’s Manual for
details). The following instruction reads from the AD7938-6:
MR = DM (ADC)
where ADC is the address of the AD7938-6.
ADSP-21xx*
WR
RD
DB0 TO DB11
D0 TO D23
A0 TO A15
DMS
IRQ2
BUSY
CONVST
DSP/USER SYSTEM
CS
WR
RD
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
DATA BUS
ADDRESS
DECODER
04
75
1-
04
5
Figure 42. Interfacing to the ADSP-21xx
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