參數(shù)資料
型號(hào)： AD7938BCPZ-6
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/32頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 8CH 625KSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 625k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 7.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 托盤(pán)
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極；4 個(gè)偽差分，單極；7 偽差分，單極
配用： EVAL-AD7938CBZ-ND - EVAL BOARD FOR AD7938
Data Sheet
AD7938-6
Rev. C | Page 23 of 32
At the end of the conversion, BUSY goes low and can be used to
activate an interrupt service routine. The CS and RD lines are
then activated in parallel to read the 12 bits of conversion data.
When power supplies are first applied to the device, a rising
edge on CONVST is necessary to put the track-and-hold into
track. The acquisition time of 125 ns minimum must be allowed
before CONVST is brought low to initiate a conversion. The
ADC then goes into hold on the falling edge of CONVST and
back into track on the 13th rising edge of CLKIN after this (see
). When operating the device in autoshutdown or
autostandby mode, where the ADC powers down at the end of
each conversion, a rising edge on the
CONVST signal is used to
power up the device.
PARALLEL INTERFACE
The AD7938-6 has a flexible, high speed, parallel interface. This
interface is 12-bits wide and is capable of operating in either
word (W/B tied high) or byte (W/B tied low) mode. The
CONVST signal is used to initiate conversions, and when
operating in autoshutdown or autostandby mode, it is used to
initiate power-up.
A falling edge on the CONVST signal is used to initiate
conversions and it puts the ADC track-and-hold into track.
Once the CONVST signal goes low, the BUSY signal goes high
for the duration of the conversion. In between conversions,
CONVST must be brought high for a minimum time of t1. This
must happen after the 14th falling edge of CLKIN; otherwise, the
conversion is aborted and the track-and-hold goes back into track.
t2
t3
t20
t14
t11
t9
t13
t12
t10
tCONVERT
tACQUISITION
tQUIET
t1
12
3
4
5
12
13
14
B
A
DATA
OLD DATA
DB0 TO DB11
RD
THREE-STATE
CS
INTERNAL
TRACK/HOLD
BUSY
CLKIN
CONVST
WITH CS AND RD TIED LOW
04
75
1-
00
4
Figure 35. AD7938-6 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/B = 1)
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