RSOURCE () 40 –45 –50 –55 –80 –75 –" />
參數(shù)資料
型號： AD7938BCPZ-6
廠商： Analog Devices Inc
文件頁數(shù)： 10/32頁
文件大小： 0K
描述： IC ADC 12BIT 8CH 625KSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 625k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 7.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 托盤
輸入數(shù)目和類型： 8 個單端，單極；4 個差分，單極；4 個偽差分，單極；7 偽差分，單極
配用： EVAL-AD7938CBZ-ND - EVAL BOARD FOR AD7938
AD7938-6
Data Sheet
Rev. C | Page 18 of 32
–
RSOURCE ()
40
–45
–50
–55
–80
–75
–70
–65
–60
–85
75
1-
0
18
–90
10
100
1k
10k
04
TH
D
(
d
B
)
FIN = 50kHz
VDD = 5V
VDD = 3V
Figure 20. THD vs. Source Impedance in Single-Ended Mode
RSOURCE ()
TH
D
(
d
B
)
–60
–80
–75
–70
–65
–100
–85
–90
–95
10
100
1k
10k
04
75
1-
0
19
FIN = 50kHz
VDD = 5V
VDD = 3V
Figure 21. THD vs. Source Impedance in Differential Mode
Figure 22 shows a graph of the THD vs. the analog input
frequency for various supplies while sampling at 625 kHz with
an SCLK of 10 MHz. In this case, the source impedance is 10 Ω.
INPUT FREQUENCY (kHz)
TH
D
(
d
B
)
–50
–60
–70
–80
–110
–100
–90
–120
0
100
400
200
300
600
500
700
04
75
1-
02
0
FSAMPLE = 625kSPS
RANGE = 0 TO VREF
VDD = 3V
SINGLE-ENDED MODE
VDD = 5V/3V
DIFFERENTIAL MODE
VDD = 5V
SINGLE-ENDED MODE
Figure 22. THD vs. Analog Input Frequency for Various Supply Voltages
ANALOG INPUTS
The AD7938-6 has software-selectable analog input
configurations. The user can choose either eight single-ended
inputs, four fully differential pairs, four pseudo differential
pairs, or seven pseudo differential inputs. The analog input
configuration is chosen by setting the MODE0/MODE1 bits in
the internal control register (see Table 9).
Single-Ended Mode
The AD7938-6 can have eight single-ended analog input
channels by setting the MODE0 and MODE1 bits in the control
register to 0. In applications where the signal source has a high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. An op amp suitable for this function is
the AD8021. The analog input range can be programmed to be
either 0 V to VREF or 0 V to 2 × VREF.
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it the correct format for the ADC.
Figure 23 shows a typical connection diagram when operating
the ADC in single-ended mode. This diagram shows a bipolar
signal of amplitude ±1.25 V being preconditioned before it is
applied to the AD7938-6. In cases where the analog input
amplitude is ±2.5 V, the 3R resistor can be replaced with a
resistor of value R. The resultant voltage on the analog input of
the AD7938-6 is a signal ranging from 0 V to 5 V. In this case,
the 2 × VREF mode can be used.
0.47F
+1.25V
VIN
R
3R
0V
–1.25V
+2.5V
0V
VIN0
VIN7
VREFOUT
AD7938-6*
*ADDITIONAL PINS OMITTED FOR CLARITY.
04
751
-03
1
Figure 23. Single-Ended Mode Connection Diagram
Differential Mode
The AD7938-6 can have four fully differential analog input
pairs by setting the MODE0 and MODE1 bits in the control
register to 0 and 1, respectively.
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 24 defines the fully differential analog
input of the AD7938-6.
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