參數(shù)資料
型號(hào)： AD7723BSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT SIGMA-DELTA 44MQFP
標(biāo)準(zhǔn)包裝： 800
位數(shù)： 16
采樣率（每秒）： 1.2M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，單極；1 個(gè)差分，雙極
配用： EVAL-AD7723CBZ-ND - BOARD EVALUATION FOR AD7723
AD7723
Rev. C | Page 20 of 32
APPLYING THE AD7723
ANALOG INPUT RANGE
The AD7723 has differential inputs to provide common-mode
noise rejection. In unipolar mode, the analog input range is 0 to
8/5 × VREF2, while in bipolar mode, the analog input range is
±4/5 × VREF2. The output code is twos complement binary in
both modes with 1 LSB = 61 V. The ideal input/output transfer
characteristics for the two modes are shown in Figure 34. In
both modes, the absolute voltage on each input must remain
within the supply range AGND to AVDD. The bipolar mode
allows either single-ended or complementary input signals.
011…111
011…110
000…010
000…001
000…000
111…111
111…110
100…000
100…001
–4/5
×V
REF2
0V
+4/5
× V
REF2 – 1LSB BIPOLAR
(0V)
(+4/5
× V
REF2)
(+8/5
× V
REF2 – 1LSB) UNIPOLAR
01186-
034
Figure 34. Bipolar (Unipolar) Mode Transfer Function
The AD7723 accepts full-scale, in-band signals. However, large
scale out-of-band signals can overload the modulator inputs.
Figure 35 shows the maximum input signal level as a function
of frequency. A minimal single-pole, RC, antialias filter set to
fCLKIN/24 allows full-scale input signals over the entire frequency
spectrum.
INPUT SIGNAL FREQUENCY RELATIVE TO
fCLKIN
0
0.5
0.02
0.04
0.06
0.08
0.10
0.12
0.14
2.2
2.1
1.3
PEAK
INPUT
(V
p-p)
1.7
1.6
1.5
1.4
1.9
1.8
2.0
VREF = 2.5V
01186-035
Figure 35. Peak Input Signal Level vs. Signal Frequency
ANALOG INPUT
The analog input of the AD7723 uses a switched capacitor
technique to sample the input signal. For the purpose of driving
the AD7723, an equivalent circuit of the analog inputs is shown
in Figure 36. For each half clock cycle, two highly linear
sampling capacitors are switched to both inputs, converting the
input signal into an equivalent sampled charge. A signal source
driving the analog inputs must be able to source this charge
while also settling to the required accuracy by the end of each
half-clock phase.
500
500
AD7723
CLKIN
VIN(+)
VIN(–)
AC
GROUND
2pF
ΦA(chǔ)
ΦB
ΦA(chǔ)
ΦB
Φ
A ΦB
Φ
A ΦB
20
19
01186-036
Figure 36. Analog Input Equivalent Circuit
DRIVING THE ANALOG INPUTS
To interface the signal source to the AD7723, at least one op
amp is generally required. Choice of op amp is critical to
achieving the full performance of the AD7723. The op amp not
only has to recover from the transient loads that the ADC
imposes on it, but it must also have good distortion
characteristics and very low input noise. Resistors in the signal
path can also add to the overall thermal noise floor,
necessitating the choice of low value resistors.
Placing an RC filter between the drive source and the ADC
inputs, as shown in Figure 37, has a number of beneficial
effects. Transients on the op amp outputs are significantly
reduced because the external capacitor now supplies the
instantaneous charge required when the sampling capacitors are
switched to the ADC input pins and input circuit noise at the
sample images is now significantly attenuated, resulting in
improved overall SNR. The external resistor serves to isolate the
external capacitor from the ADC output, thus improving op
amp stability while also isolating the op amp output from any
remaining transients on the capacitor. By experimenting with
different filter values, the optimum performance can be
achieved for each application. As a guideline, the RC time
constant (R × C) should be less than a quarter of the clock
period to avoid nonlinear currents from the ADC inputs being
stored on the external capacitor and degrading distortion. This
restriction means that this filter cannot form the main antialias
filter for the ADC.
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