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參數(shù)資料
| 型號(hào)： | AD7467BRT |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | MO-178AB, SOT-23, 6 PIN |
| 文件頁(yè)數(shù)： | 21/24頁(yè) |
| 文件大小： | 327K |
| 代理商： | AD7467BRT |
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–6–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7466/AD7467/AD7468
Limit at TMIN, TMAX
Parameter
AD7466/AD7467/AD7468
Units
Description
fSCLK
2
10
kHz min3
3.4
MHz max
tCONVERT
16 x tSCLK
AD7466
12 x tSCLK
AD7467
10 x tSCLK
AD7468
tQUIET
T B D
ns min
Minimum Quiet Time required between Bus
Relinquish and start of next conversion
t1
T B D
ns min
Minimum
CS Pulsewidth
t2
10
ns min
CS to SCLK Setup Time
t3
4
T B D
ns max
Delay from
CS Until SDATA 3-State Disabled
t4
4
T B D
ns max
Data Access Time After SCLK Falling Edge
t5
0.4tSCLK
ns min
SCLK Low Pulse Width
t6
0.4tSCLK
ns min
SCLK High Pulse Width
t7
T B D
ns min
SCLK to Data Valid Hold Time
t8
5
T B D
ns max
SCLK falling Edge to SDATA High Impedance
tpower-up
TBD
s max
Power up time from Power down.
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage
level of
TBD
Volts.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Minimum
fsclk at which specifications are guaranteed.
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vih or Vil voltage.
5t
8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the
timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
Specifications subject to change without notice.
Figure 1. Load Circuit for Digital Output Timing
Specifications
+1.6V
IOL
200A
IOH
TO
OUTPUT
PIN
CL
50pF
TIMING SPECIFICATIONS1 (VDD = +1.6 V to +3.6 V; TA = TMIN to TMAX, unless otherwise noted.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7467BRT-R | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRT-R2 | 功能描述:IC ADC 10BIT 1.6V LP SOT23-6 RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7467BRT-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRT-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRTZ-R | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
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