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參數(shù)資料
| 型號： | AD7467BRT |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | MO-178AB, SOT-23, 6 PIN |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 327K |
| 代理商： | AD7467BRT |
–19–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7466/AD7467/AD7468
The average power consumption includes the power dissipated when the part is converting and the power dissipated when
the part is in power down mode. The average power dissipated during conversion is calculated as the percentage of the
cycle time spent when converting multiplied by the peak current during conversion. The average power dissipated when
in power down mode is calculated as the percentage of the cycle time spent in power down mode multiplied by the
current figure for power down mode. In order to obtain the value for the average power, these terms must be multiplied
by the voltage.
Considering the peak current for each SCLK frequency for VDD= 1.8V,
Power consumption A= ((4.7/20) x 186
A + (15.3/20) x 1A) x 1.8V = (43.71+0.765) A x1.8V = 80W = 0.08 mW
Power consumption B= ((13/20) x 108
A + (7/20) x 1A) x 1.8V = (70.2+0.35) A x1.8V = 126.99W = 0.127 mW
It can be concluded that for a fixed throughput rate, the average power consumption drops as the SCLK frequency
increases.
Power Consumption Example 2er Coxample 2
This example shows that for a fixed SCLK frequency, as the throughput rate decreases the average power consumption
drops. From Figure 12, for SCLK = 3.4 MHz, Throughput A = 100KSPS (which gives a cycle time of 10
s) and
Throughput B = 50KSPS (which gives a cycle time of 20
s) the following values can be obtained:
Conversion time A= 16 x (1/SCLK) = 4.7
s (47% of the cycle time for a throughput of 100KSPS)
Power down time A= (1/throughput A) - Conversion time A = 10
s - 4.7s = 5.3s (53% of the cycle time)
Conversion time B= 16 x (1/SCLK) = 4.7
s (23.5% of the cycle time for a throughput of 50KSPS)
Power down time B= (1/throughput B) - Conversion time B = 20
s - 4.7s = 15.3s (76.5% of the cycle time)
The average power consumption is calculated as it has been explained in the Power Consumption Example1, considering
the peak current for a 3.4MHz SCLK frequency for VDD= 1.8V.
Power consumption A= ((4.7/10) x 186
A + (5.3/10) x 1A)x 1.8V= (87.42+0.53)A x1.8V= 158.3W= 0.156 mW
Power consumption B= ((4.7/20) x 186
A + (15.3/20) x 1A) x 1.8V= (43.7+0.765)A x1.8V = 80W = 0.08 mW
It can be concluded that for a fixed SCLK frequency, the average power consumption
drops as the throughput rate
decreases.
SERIAL INTERFACE
Figures 14, 15, 16 show the detailed timing diagram for
serial interfacing to the AD7466/AD7467/AD7468.The
serial clock provides the conversion clock and also con-
trols the transfer of information from the ADC during a
conversion.
On the
CS falling edge the part begins to power up. The
falling edge of
CS puts the Track and Hold into track
mode and takes the bus out of three-state. The conversion
is also initiated at this point. On the third SCLK falling
edge after the
CS falling edge, the part should be fully
powered up, as shown in Figure 14 at point B, and the
Track and Hold will return to hold.
For the AD7466, on the 16th SCLK falling edge the
SDATA line will go back into three-state and the part will
enter power down. If the rising edge of
CS occurs before
16 SCLKs have elapsed then the conversion will be
terminated, the SDATA line will go back into three-state
and the part will enter power down, otherwise SDATA
returns to three-state on the 16th SCLK falling edge as
shown in Figure 14. Sixteen serial clock cycles are re-
quired to perform the conversion process and to access
data from the AD7466.
Figure 14. AD7466 Serial Interface Timing Diagram
&6
SCLK
1
5
13
15
4 LEADING ZERO’S
3-S TATE
t4
2
34
16
t
5
t3
tQUIET
t
CONVE RT
t2
3-STATE
DB11
DB10
DB2
DB0
t
6
t7
t8
14
ZERO
Z
B
DB1
SDATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7468BRT | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7466 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7467 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7468 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD746A | Dual Precision, 500 ns Settling, BiFET Op Amp |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7467BRT-R | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRT-R2 | 功能描述:IC ADC 10BIT 1.6V LP SOT23-6 RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7467BRT-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRT-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRTZ-R | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
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