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參數(shù)資料
| 型號(hào)： | AD7467BRT |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | MO-178AB, SOT-23, 6 PIN |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 327K |
| 代理商： | AD7467BRT |
–21–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7466/AD7467/AD7468
MICROPROCESSOR INTERFACING
The serial interface on the AD7466/AD7467/AD7468
allows the part to be directly connected to a range of many
different microprocessors. This section explains how to
interface the AD7466/AD7467/AD7468 with some of the
more common microcontroller and DSP serial interface
protocols.
AD7466/67/68 to TMS320C541 Interface
The serial interface on the TMS320C541 uses a
continuous serial clock and frame synchronization signals
to synchronize the data transfer operations with peripheral
devices like the AD7466/67/68. The
CS input allows easy
interfacing between the TMS320C541 and the AD7466/
67/68 without any glue logic required. The serial port of
the TMS320C541 is set up to operate in burst mode
(FSM=1 in the Serial Port Control register, SPC) with
internal CLKX (MCM=1 in the SPC register) and
interanl frame signal (TXM = 1 in the SPC register), so
both pins are configured as outputs. For the AD7466 the
word length should be set to 16 bits (FO=0 in the SPC
register). This DSP only allows frames with a word length
of 16 or 8 bits. Therefore, for the AD7467 and AD7468
where 14 and 12 bits are required, the FO bit would be
set up to 16 bits also. In these cases, the user should keep
in mind that, the last two and four bits for the AD7467
and AD7468 respectively, will be invalid data as the
SDATA line goes back into three-state on the 14th and
12th SCLK falling edge.
To summarise, the values in the SPC register are:
FO=0
FSM=1
MCM=1
TXM=1
The connection diagram is shown in Figure 17. It should
be noted that for signal processing applications, it is
imperative that the frame synchronisation signal from the
TMS320C541 will provide equidistant sampling.
AD7466/67/68*
SDATA
SCLK
&6
TMS320C541*
*Additional Pins omitted for clarity
CLKX
CLKR
DR
FSX
FSR
Figure 17. Interfacing to the TMS320C541
AD7466/67/68 to ADSP218x
The ADSP218x family of DSPs are interfaced directly to
the AD7466/67/68 without any glue logic required. The
SPORT control register should be set up as follows:
TFSW= RFSW= 1, Alternate Framing
INVRFS= INVTFS= 1, Active Low Frame Signal
DTYPE= 00, Right Justify Data
ISCLK= 1, Internal Serial Clock
TFSR= RFSR= 1, Frame Every Word
IRFS= 0, it sets up RFS as an Input
ITFS= 1, it sets up TFS as an Output
SLEN= 1111, 16 bits for the AD7466
SLEN= 1101, 14 bits for the AD7467
SLEN= 1011, 12 bits for the AD7468
The connection diagram is shown in Figure 18. The
ADSP218x has the TFS and RFS of the SPORT tied
together, with TFS set as an output and RFS set as an
input. The DSP operates in Alternate Framing Mode and
the SPORT control register is set up as described. The
frame synchronisation signal generated on the TFS is tied
to
CS and as with all signal processing applications
equidistant sampling is necessary. However, in this ex-
ample, the timer interrupt is used to control the sampling
rate of the ADC and, under certain conditions, equidistant
sampling may not be achieved.
The timer registers etc., are loaded with a value which
will provide an interrupt at the required sample interval.
When an interrupt is received, a value is transmitted with
TFS/DT (ADC control word). The TFS is used to
control the RFS and hence the reading of data. The
frequency of the serial clock is set in the SCLKDIV
register. When the instruction to transmit with TFS is
given, i.e. AX0= TX0, the state of the SCLK is checked.
The DSP will wait until the SCLK has gone high, low
and high before transmission will start. If the timer and
SCLK values are chosen such that the instruction to
transmit occurs on or near the rising edge of SCLK, the
data may be transmitted or it may wait until the next clock
edge.
For example, the ADSP2111 has a master clock frequency
of 16MHz. If the SCLKDIV register is loaded with the
value 3 then a SCLK of 2MHz is obtained, and 8 master
clock periods will elapse for every one SCLK period. If
the timer registers are loaded with the value 803, 100.5
SCLKs will occur between interrupts and subsequently
between transmit instructions. This situation will result in
non-equidistant sampling as the transmit instruction is
occuring on a SCLK edge. If the number of SCLKs
between interrupts is a whole integer figure of N then
equidistant sampling will be implemented by the DSP.
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PDF描述 |
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| AD7468BRT | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7466 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7467 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7468 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD7467BRT-R | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRT-R2 | 功能描述:IC ADC 10BIT 1.6V LP SOT23-6 RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7467BRT-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRT-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
| AD7467BRTZ-R | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 V, Micropower 12-/10-/8-Bit ADCs |
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