參數(shù)資料
型號(hào)： AD73322LYRZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 31/48頁(yè)
文件大小： 0K
描述： IC ANALOG FRONT END DUAL 28-SOIC
標(biāo)準(zhǔn)包裝： 27
位數(shù)： 16
通道數(shù)： 4
功率（瓦特）： 73mW
電壓 - 電源，模擬： 2.7 V ~ 5.5 V
電壓 - 電源，數(shù)字： 2.7 V ~ 5.5 V
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
AD73322L
Rev. A | Page 37 of 48
DSP PROGRAMMING CONSIDERATIONS
This section discusses how the serial port of the DSP should
be configured and the implications of whether Rx and Tx
interrupts should be enabled.
DSP SPORT CONFIGURATION
Following are the key settings of the DSP SPORT required for
the successful operation with the AD73322L:
Configure for external SCLK
Serial word length = 16 bits
Transmit and receive frame syncs required with every word
Receive frame sync is an input to the DSP
Transmit frame sync is an:
Input—in frame sync loop-back mode
Output—in nonframe sync loop-back mode
Frame syncs occur one SCLK cycle before the MSB of the
serial word
Frame syncs are active high
DSP SPORT INTERRUPTS
If SPORT interrupts are enabled, it is important to note that
the active signals on the frame sync pins do not necessarily
correspond in real time to when SPORT interrupts are
generated.
On ADSP-21xx processors, it is necessary to enable SPORT
interrupts and use interrupt service routines (ISRs) to handle
Tx/Rx activity, while on the TMS320CSx processors, it is
possible to poll the status of the Rx and Tx registers. This means
that Rx/Tx activity can be monitored using a single ISR that
would ideally be the Tx ISR because the Tx interrupt typically
occurs before the Rx ISR.
DSP SOFTWARE CONSIDERATIONS WHEN
INTERFACING TO THE AD73322L
When choosing the operating mode and hardware config-
uration of the AD73322L, be aware of their implications for
DSP software operation. The user has the flexibility of choosing
from either FSLB or nonFSLB when deciding on DSP-to-AFE
connectivity. There is also a choice to be made between using
autobuffering of input and output samples, or simply choosing
to accept them as individual interrupts. Because most modern
DSP engines support these modes, this section discusses these
topics in a generic DSP sense.
OPERATING MODE
The AD73322L supports two basic operating modes: frame
sync loop back (fslb) and nonfslb (see the Interfacing section).
As described previously, FSLB has some limitations when used
in mixed mode but is very suitable for use with the
autobuffering feature that is offered on many modern DSPs.
Autobuffering allows the user to specify the number of input or
output words (samples) that are transferred before a specific Tx
or Rx SPORT interrupt is generated. Given that the AD73322L
outputs two sample words per sample period, it is possible,
using auto-buffering, to have the DSP’s SPORT generate a single
interrupt on receipt of the second of the two sample words.
Additionally, both samples could be stored in a data buffer
within the data memory store. This technique has the advantage
of reducing the number of both Tx and Rx SPORT interrupts to
a single one at each sample interval. The user also knows where
each sample is stored. The alternative is to handle a larger
number of SPORT interrupts (twice as many in the case of a
single AD73322L) while also having some status flags to
indicate the origin and destination of each new sample.
MIXED-MODE OPERATION
To take full advantage of mixed-mode operation, configure the
DSP/Codec interface in nonFSLB and disable autobuffering.
This allows a variable number of words to be sent to the
AD73322L in each sample period—the extra words being
control words that are typically used to update gain settings in
adaptive control applications. The recommended sequence for
updating control registers in mixed mode is to send the control
word(s) first before the DAC update word.
It is possible to use mixed-mode operation when configured
in FSLB, but it is necessary to replace the DAC update with a
control word write in each sample period. This may cause some
discontinuity in the output signal due to a sample point being
missed and the previous sample being repeated. However, this
may be acceptable in some cases as the effect may be masked by
gain changes, etc.
INTERRUPTS
The AD73322L transfers and receives information over the
serial connection from the DSP’s SPORT. This occurs following
reset—during the initialization phase—and in both data mode
and mixed mode. Each transfer of data to or from the DSP can
cause a SPORT interrupt to occur. However even in FSLB
configuration where serial transfers in and out of the DSP are
synchronous, Tx and Rx interrupts do not occur at the same
time due to the way that Tx and Rx interrupts are generated
internally within the DSP’s SPORT. This is especially important
in time-critical, control loop applications where it may be
necessary to use Rx interrupts only, as the relative positioning of
the Tx interrupts relative to the Rx interrupts in a single sample
interval are not suitable for quick update of new DAC positions.
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