參數(shù)資料
型號(hào)： AD73322LYRZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 13/48頁(yè)
文件大小： 0K
描述： IC ANALOG FRONT END DUAL 28-SOIC
標(biāo)準(zhǔn)包裝： 27
位數(shù)： 16
通道數(shù)： 4
功率（瓦特）： 73mW
電壓 - 電源，模擬： 2.7 V ~ 5.5 V
電壓 - 電源，數(shù)字： 2.7 V ~ 5.5 V
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
AD73322L
Rev. A | Page 20 of 48
DAC ADVANCE REGISTER
The loading of the DAC is internally synchronized with the
unloading of the ADC data in each sampling interval. The
default DAC load event happens one SCLK cycle before the
SDOFS flag is raised by the ADC data being ready. However,
this DAC load position can be advanced before this time by
modifying the contents of the DAC advance field in Control
Register E (CRE:0–4). The field is five bits wide, allowing
31 increments of weight 1/(FS × 32), as shown in Table 15.
The sample rate, fS, depends on the setting of both the MCLK
divider and the sample rate divider, as shown in Table 12 and
Table 14. In certain circumstances this DAC update adjustment
can reduce the group delay when the ADC and DAC are used to
process data in series. For more information about how the
DAC advance register can be used, see the section Configuring
NOTE: The DAC advance register should not be changed while
the DAC section is powered up.
Table 15. DAC Timing Control
DA4
DA3
DA2
DA1
DA0
Time Advance
0
0 s
0
1
1/(FS × 32) s
0
1
0
2/(FS × 32) s
1
0
30/(FS × 32) s
1
31/(FS × 32) s
Table 16. Control Register Map
Address (Binary)
Name
Description
Type
Width
Reset Setting (Hex)
000
CRA
Control Register A
R/W
8
0x00
001
CRB
Control Register B
R/W
8
0x00
010
CRC
Control Register C
R/W
8
0x00
011
CRD
Control Register D
R/W
8
0x00
100
CRE
Control Register E
R/W
8
0x00
101
CRF
Control Register F
R/W
8
0x00
110
CRG
Control Register G
R/W
8
0x00
111
CRH
Control Register H
R/W
8
0x00
Table 17. Control Word Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C/D
R/W
Device Address
Register Address
Register Data
Control
Frame
Description
Bit 15
Control/Data
When set high, this bit signifies a control word in program or mixed program/data modes. When set
low, it signifies a data-word in mixed program/data mode or an invalid control word in program mode.
Bit 14
Read/Write
When set low, this bit tells the device that the data field is to be written to the register selected by the
register field setting, provided the address field is zero. When set high, it tells the device that the
selected register is to be written to the data field in the input serial register and that the new control
word is to be output from the device via the serial output.
Bits 13 to 11
Device Address
This 3-bit field holds the address information. Only when this field is zero is a device selected. If the
address is not zero, it is decremented and the control word is passed out of the device via the serial
output.
Bits 10 to 8
Register Address
This 3-bit field is used to select one of the eight control registers on the AD73322L.
Bits 7 to 0
Register Data
This 8-bit field holds the data that is to be written to or read from the selected register provided the
address field is zero.
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