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參數(shù)資料
| 型號(hào)： | AD7298BCPZ-RL7 |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 15/25頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SPI/SRL 8CH 20LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 22.7mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-WQ（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類(lèi)型： | 8 個(gè)單端，單極 |
| 其它名稱(chēng)： | AD7298BCPZ-RL7DKR |
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AD7298
Rev. B | Page 21 of 24
SERIAL INTERFACE
The CS going low provides the first address bit to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges, beginning with a second
address bit. Thus, the first falling clock edge on the serial clock
has the first address bit provided for reading and also clocks out
the second address bit. The three remaining address bits and
12 data bits are clocked out by subsequent SCLK falling edges.
The final bit in the data transfer is valid for reading on the
16th falling edge having been clocked out on the previous (15th)
falling edge.
Figure 30 shows the detailed timing diagram for the serial
interface to the AD7298. The serial clock provides the conver-
sion clock and controls the transfer of information to and from
the AD7298 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires 16 SCLK cycles to complete. The track-and-hold
goes back into track on the 14th SCLK falling edge as shown in
at Point B. On the 16th SCLK falling edge or on the
rising edge of
CS , the DOUT line goes back into three-state.
In applications with a slower SCLK, it may be possible to read
in data on each SCLK rising edge depending on the SCLK
frequency. The first rising edge of SCLK after the CS falling
edge would have the first address bit provided, and the 15th
rising SCLK edge would have last data bit provided.
If the rising edge of CS occurs before 16 SCLKs have elapsed,
the conversion is terminated, the DOUT line goes back into tri-
state, and the control register is not updated; otherwise, DOUT
returns to three-state on the 16th SCLK falling edge. Sixteen serial
clock cycles are required to perform the conversion process and
to access data from the AD7298.
Writing information to the control register takes place on the
first 16 falling edges of SCLK in a data transfer, assuming the MSB
(that is, the WRITE bit) has been set to 1. The 16-bit word read
from the AD7298 always contains four channel address bits that
the conversion result corresponds to, followed by the 12-bit
conversion result.
For the AD7298, four-channel address bits (ADD3 to ADD0)
that identify which channel the conversion result corresponds
to precede the 12 bits of data (see Table 9).
CS
DOUT
DIN
t2
t3
t9
t10
t4
t7
tACQUISITION
t8
tQUIET
t5
t6
SCLK
THREE-
STATE
THREE-
STATE
ADD3
WRITE
REPEAT
CH0
CH1
CH2
CH3
EXT_REF
PPD
TSENSEAVG
ADD2
12345
13
14
B
15
16
ADD1
ADD0
DB11
DB10
DB2
DB1
DB0
08
75
4-
01
4
Figure 30. Serial Interface Timing Diagram
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