參數(shù)資料
型號(hào)： AD7298BCPZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/25頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT SPI/SRL 8CH 20LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 22.7mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 20-LFCSP-WQ（4x4）
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 8 個(gè)單端，單極
其它名稱： AD7298BCPZ-RL7DKR
AD7298
Rev. B | Page 18 of 24
CS
SCLK
DOUT
DIN
112
16
1
16
1
16
CONVERSION RESULT
FOR CHANNEL 0
CONVERSION RESULT
FOR CHANNEL 1
INVALID DATA
NO WRITE TO THE
CONTROL REGISTER
NO WRITE TO THE
CONTROL REGISTER
DATA WRITTEN TO CONTROL
REGISTER CH 0, CH 1, AND CH 2
SELECTED: REPEAT = 1
CS
SCLK
DOUT
DIN
116
CONVERSION RESULT
FOR CHANNEL 0
CONVERSION RESULT
FOR CHANNEL 2
NO WRITE TO THE
CONTROL REGISTER
NO WRITE TO THE
CONTROL REGISTER
NO WRITE TO THE
CONTROL REGISTER
0
875
4-
0
1
Figure 27. Configuring a Conversion and Read in Repeat Mode
REPEAT OPERATION
The REPEAT bit in the control register allows the user to select
a sequence of channels on which the AD7298 continuously
converts. When the REPEAT bit is set in the control register,
the AD7298 continuously cycles through the selected channels
in ascending order, beginning with the lowest channel and
converting all channels selected in the control register. On
completion of the sequence, the AD7298 returns to the first
selected channel in the control register and recommences the
sequence.
The conversion sequence of the selected channels in the repeat
mode of operation continues until such time as the control
register of the AD7298 is reprogrammed. If the TSENSE bit is
selected in the control register, then the temperature conversion
will be available for conversion after the last analog input
channel in the sequence has been converted. It is not necessary
to write to the control register once a repeat operation is
initiated unless a change in the AD7298 configuration is
required. The WRITE bit must be set to zero or the DIN line
tied low to ensure that the control register is not accidentally
overwritten, or the automatic conversion sequence interrupted.
A write to the control register during the repeat mode of
operation resets the cycle even if the selected channels are
unchanged. Thus, the next conversion by the AD7298 after
a write operation will be the first selected channel in the
sequence.
To select a sequence of channels, the associated channel bit
must be set to a logic high state (1) for each analog input whose
conversion is required. For example, if the REPEAT bit = 1,
then CH0, CH1, and CH2 = 1. The VIN0 analog input is
converted on the first CS falling edge following the write to
the control register, the VIN1 channel is converted on the
subsequent CS falling edge, and the VIN0 conversion result is
available for reading. The third CS falling edge following the
write operation initiates a conversion on VIN2 and has the VIN1
result available for reading. The AD7298 operates with one
cycle latency, thus the conversion result corresponding to each
conversion is available one serial read cycle after the cycle in
which the conversion is initiated.
This mode of operation simplifies the operation of the device by
allowing consecutive channels to be converted without having
to reprogram the control register or write to the part on each
serial transfer. Figure 27 illustrates how to set up the AD7298
to continuously convert on a particular sequence of channels.
To exit the repeat mode of operation and revert back to the
traditional mode of operation of a multichannel ADC, ensure
that the REPEAT bit = 0 on the next serial write.
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