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參數(shù)資料
| 型號： | AD7183 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| 中文描述： | 先進的視頻解碼器，10位ADC和組件輸入支持 |
| 文件頁數(shù)： | 30/41頁 |
| 文件大小： | 484K |
| 代理商： | AD7183 |
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REV. 0
–30–
ADV7183
Table XXXII. Pixel Delay Control Register (Subaddress 27)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
RESERVED
CTA[2:0]
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
RESERVED
1
SWPC
2
0
1
NOTES
1
Chroma Timing Adjust. Allows a specified timing difference between the luma and chroma samples.
2
Allows the Cr and Cb samples to be swapped.
0
0
0
Set to Zero
Not Valid
Chroma + 2 Pixel (Early)
Chroma + 1 Pixel (Early)
No Delay
Chroma – 1 Pixel (Late)
Chroma – 2 Pixel (Late)
Chroma – 3 Pixel (Late)
Not Valid
Set to One
No Swapping
Swap the Cr and Cb Values
0
1
0
1
0
1
0
1
Table XXXIII. Manual Clock Control 1 Register (Subaddress 28)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
CLKVAL[17:16]
1
RESERVED
1
1
CLKMANE
2
0
1
FIX27E
3
0
1
NOTES
1
If enabled via CLKMANE, CLKVAL[17:0] determines the fixed output frequency. On the LLC, LLC2, and LLCREF pins.
2
Clock Generator Manual Enable. Allows the analog clock generator to produce a fixed clock frequency that is not dependent on the video signal.
3
Allows the o/p of fixed 27 MHz crystal clock via LLC, LLC2, and LLCREF o/p pins.
X
X
1
1
Set to Default
Output Frequency Set by Video
Frequency Set by CLKVAL[17:0]
Output Frequency Set by Clock Generator
Output 27 MHz Fixed
Table XXXIV. Manual Clock Control 2 Register (Subaddress 29)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
CLKVAL[15:8]
*
X
X
X
X
*
If enabled via CLKMANE, CLKVAL[17:0] determines the fixed output frequency. On the LLC, LLC2, and LLCREF pins.
X
X
X
X
Table XXXV. Manual Clock Control 3 Register (Subaddress 2A)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
CLKVAL[7:0]
*
X
X
X
X
*
If enabled via CLKMANE, CLKVAL[17:0] determines the fixed output frequency. On the LLC, LLC2, and LLCREF pins.
X
X
X
X
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