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| 型號： | AD7183 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| 中文描述： | 先進(jìn)的視頻解碼器，10位ADC和組件輸入支持 |
| 文件頁數(shù)： | 24/41頁 |
| 文件大?。?/td> | 484K |
| 代理商： | AD7183 |
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REV. 0
–24–
ADV7183
Table IX. Extended Output Control Register (Subaddress 04)
Bit Description
RANGE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
1
0
1
CCIR-Compliant
Fill Whole Accessible Range
RESERVED
DDOS[2:0]
2
BT656-4
1
1
0
0
0
0
No Additional Data
BT656-3-Compatible
BT656-4-Compatible
3
4
0
1
NOTES
1
Allows the user to select the range of output values. Can be CCIR601-compliant or fill the whole accessible number range.
2
D Data Output Selection. If the 100-pin package is used, the 12 additional pins can output additional data.
3
12 Pins Three-State
4
Allows the user to select an output mode that is compatible with BT656-4 or BT656-3.
Table X. General-Purpose Output Register (Subaddress 05)
Bit Description
GPO[3:0]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
0
1
0
0
User Programmable
HD Test Pattern Off
GPO[1:0] Three-Stated
GPO[1:0] Enabled
GPO[3:2] Three-Stated
GPO[3:2] Enabled
Decode and Output Color During VBI
Blank Cr and Cb Data During VBI
GPO[0] Pin Function
6
GPO[0] Shows HLOCK Status
6
GPEL
2
0
1
GPEH
3
0
1
BL_C_VBI
4
0
1
HL_EN
5
0
1
NOTES
1
Pixel Data Valid Off. These general-purpose output pins may be programmed by the user but are only available in selected output modes OF_SEL[3:0] and when the
output drivers are enabled using GPEL, GPEH, and HL_Enable bits.
2
General Purpose Enable Low. Enables the output drivers for the general-purpose outputs Bits 0 and 1.
3
General Purpose Enable High. Enables the output drivers for the general-purpose outputs Bits 2 and 3.
4
Blank Chroma During VBI.
5
Hlock Enable. This bit causes the GPO[0] pin to output Hlock instead of GPO[0]. Only available in certain output modes.
6
GPO lower bits must be enabled GPEL. Disabled.
Table XI. FIFO Control Register (Subaddress 07)
Bit Description
FFM[4:0]
FR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
0
1
0
1
0
1
0
1
0
0
User Programmable
Normal Operation
FIFO Reset
No Auto Reset
Auto Reset
Synchronous to CLKIN
Synchronous to 27 MHz
2
3
AFR
4
FFST
5
NOTES
1
FIFO Flag Margin. Allows the user to program the location at which the FIFO flags AEF and AFF.
2
FIFO Reset. Setting this bit will cause the FIFO to reset.
3
Bit is auto cleared.
4
Automatic FIFO Reset. Setting this bit will cause the FIFO to automatically reset at the end of each field of video.
5
FIFO Flag Self Time. Sets whether the FIFO flags AEF, AFF, and HFF are output synchronous to the external CLKIN of the 27 MHz internal clock.
Table XII. Contrast Register (Subaddress 08)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
CON[7:0]
*
1
0
0
0
*
Contrast Adjust. This is the user control for contrast adjustment.
0
0
0
0
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