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| 型號(hào)： | AD7183 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| 中文描述： | 先進(jìn)的視頻解碼器，10位ADC和組件輸入支持 |
| 文件頁(yè)數(shù)： | 19/41頁(yè) |
| 文件大?。?/td> | 484K |
| 代理商： | AD7183 |
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REV. 0
ADV7183
–19–
REGISTER ACCESSES
The MPU can write to or read from all of the registers of the
ADV7183 except the subaddress register, which is a write only
register. The subaddress register determines which register the
next read or write operation accesses. All communications with
the part through the bus start with an access to the subaddress
register. Then a read/write operation is performed from/to the
target address which then increments to the next address until a
stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register in terms of its
configuration.
Subaddress Register (SR7–SR0)
The communications register is an 8-bit write only register. After the
part has been accessed over the bus and a read/write operation is
selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.
Table II shows the various operations under the control of the
subaddress register. Zero should always be written to SR7–SR6.
Register Select (SR5–SR0)
These bits are set up to point to the required starting address.
Register Name
Addr (Hex)
BASIC BLOCK
Input Control
Video Selection
Video Enhancement Control
Output Control
Extended Output Control
General-Purpose Output
Reserved
FIFO Control
Contrast Control
Saturation Control
Brightness Control
Hue Control
Default Value Y
Default Value C
Temporal Decimation
Power Management
Status Register
Info Register
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
Register Name
Addr (Hex)
ADVANCED BLOCK
Reserved
Analog Control (Internal)
Analog Clamp Control
Digital Clamp Control 1
Digital Clamp Control 2
Shaping Filter Control
Reserved
Comb Filter Control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Color Subcarrier Control 1
Color Subcarrier Control 2
Color Subcarrier Control 3
Color Subcarrier Control 4
Pixel Delay Control
Manual Clock Control 1
Manual Clock Control 2
Manual Clock Control 3
Auto Clock Control
AGC Mode Control
Chroma Gain Control 1
Chroma Gain Control 2
Luma Gain Control 1
Luma Gain Control 2
Manual Gain Shadow Control 1
Manual Gain Shadow Control 2
Misc Gain Control
HSync Position Control 1
HSync Position Control 2
HSync Position Control 3
Polarity Control
Reserved
Reserved
Reserved
Reserved
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
44
45
F1
F2
SDATA
SCLOCK
1
–
7
8
9
1
–
7
8
9
1
–
7
8
9
START ADDR R/
W
ACK SUB ADDR
ACK
DATA
ACK
STOP
S
P
Figure 29. Bus Data Transfer
Table II. Subaddress Register
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